From WikiChip
Difference between revisions of "phytium/feiteng/ft-2000+-64"
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|family=FeiTeng | |family=FeiTeng | ||
|series=FT-2000+ | |series=FT-2000+ | ||
− | |frequency=2, | + | |frequency=2,300 MHz |
|isa=ARMv8.0 | |isa=ARMv8.0 | ||
|isa family=ARM | |isa family=ARM | ||
|microarch=Mars II | |microarch=Mars II | ||
+ | |microarch 2=Xiaomi | ||
|core name=FTC-662 | |core name=FTC-662 | ||
|process=16 nm | |process=16 nm | ||
Line 46: | Line 47: | ||
== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-3200 |
|ecc=Yes | |ecc=Yes | ||
|controllers=8 | |controllers=8 | ||
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|bandwidth dchan=35.76 GiB/s | |bandwidth dchan=35.76 GiB/s | ||
|bandwidth qchan=71.53 GiB/s | |bandwidth qchan=71.53 GiB/s | ||
+ | |bandwidth hchan=107.3 GiB/s | ||
|bandwidth ochan=143.1 GiB/s | |bandwidth ochan=143.1 GiB/s | ||
− | |||
}} | }} | ||
Latest revision as of 04:41, 17 July 2023
Edit Values | |
FT-2000+/64 | |
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General Info | |
Designer | Phytium |
Manufacturer | TSMC |
Model Number | FT-2000+/64 |
Market | Server |
Introduction | 2019 (announced) 2019 (launched) |
General Specs | |
Family | FeiTeng |
Series | FT-2000+ |
Frequency | 2,300 MHz |
Microarchitecture | |
ISA | ARMv8.0 (ARM) |
Microarchitecture | Mars II, Xiaomi |
Core Name | FTC-662 |
Process | 16 nm |
Transistors | 6,000,000,000 |
Technology | CMOS |
Die | 370 mm² |
Word Size | 64 bit |
Cores | 64 |
Threads | 64 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 96 W |
Packaging | |
Package | FCBGA-3576 (BGA) |
Dimension | 61 mm × 61 mm |
Contacts | 3576 |
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Succession | |
FT-2000+/64 is a 64 core ARM server SoC designed by Phytium and introduced in 2019. Fabricated on TSMC's 16 nm process, the chip operates at up 2.3 GHz with a TDP of 96 W. This chip is designed for server, communication, and infrastructure applications.
Contents
Cache[edit]
- Main article: Mars II § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Die[edit]
- Main article: Mars II § Die
Facts about "FT-2000+/64 - Phytium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | FT-2000+/64 - Phytium#io + |
back image | ![]() |
base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
core count | 64 + |
core name | FTC-662 + |
designer | Phytium + |
die area | 370 mm² (0.574 in², 3.7 cm², 370,000,000 µm²) + |
family | FeiTeng + |
first announced | 2019 + |
first launched | 2019 + |
full page name | phytium/feiteng/ft-2000+-64 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | ARMv8.0 + |
isa family | ARM + |
l1$ size | 4,096 KiB (4,194,304 B, 4 MiB) + |
l1d$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
l1i$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
l2$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
ldate | 2019 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Server + |
max cpu count | 1 + |
max memory bandwidth | 143.1 GiB/s (146,534.4 MiB/s, 153.652 GB/s, 153,652.455 MB/s, 0.14 TiB/s, 0.154 TB/s) + |
max memory channels | 8 + |
max pcie lanes | 33 + |
microarchitecture | Mars II + and Xiaomi + |
model number | FT-2000+/64 + |
name | FT-2000+/64 + |
package | FCBGA-3576 + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
series | FT-2000+ + |
smp max ways | 1 + |
supported memory type | DDR4-3200 + |
tdp | 96 W (96,000 mW, 0.129 hp, 0.096 kW) + |
technology | CMOS + |
thread count | 64 + |
transistor count | 6,000,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |