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Difference between revisions of "intel/xeon silver"
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(changed 768 GiB hexa-channel DDR4-2133ECC memory. to 768 GiB hexa-channel DDR4-2400 ECC memory. because al th CPU support 2400)
(→‎4200-Series (Cascade Lake))
 
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== Members ==
 
== Members ==
−
=== Skylake ===
+
=== 4100-Series (Skylake) ===
 
{{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}}
 
{{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}}
−
Introduced in July 2017, the {{intel|Skylake (server)|Skylake|l=arch}}-based Xeon Silver microprocessors are all dual-socket [[multiprocessors]] with up to [[12 cores]] and 24 threads. Additionally, all Xeon Silver processors support:
+
First-generation Xeon Silver processors were introduced in July 2017. Those chips were fabricated on a enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture which brought a {{intel|Skylake (Server)#Key changes from Broadwell|l=arch|relatively large}} SoC design change from the prior Xeon families. Those processors were the first to move to a {{intel|mesh interconnect}} which introduced a tile-based architecture, bringing the first implementation of {{x86|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the Silver 4100-series microprocessors feature dual-socket capabilities with up to [[12 cores]] and 24 threads. Additionally, all Xeon Silver processors support:
  
−
* '''TDP:''' 85 W, 70 W
+
* '''Proc:''' [[14 nm process]]
 +
* '''TDP:''' 70 W, 85 W
 
* '''Mem:''' 768 GiB hexa-channel DDR4-2400 ECC memory.
 
* '''Mem:''' 768 GiB hexa-channel DDR4-2400 ECC memory.
−
* '''I/O:''' 48 PCIe 3 lanes
+
* '''I/O:''' 48 PCIe Gen 3.0 lanes
−
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL)
+
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}})
 
* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
 
* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
  
Line 55: Line 56:
 
{{comp table start}}
 
{{comp table start}}
 
<table class="comptable sortable tc4 tc5">
 
<table class="comptable sortable tc4 tc5">
−
<tr class="comptable-header"><th>&nbsp;</th><th colspan="20">List of Skylake-based Xeon Silver Processors</th></tr>
+
{{comp table header|main|9:List of Skylake-based Xeon Silver Processors}}
−
<tr class="comptable-header"><th>&nbsp;</th><th colspan="7">Main processor</th><th colspan="2">Cache</th><th colspan="2">Memory</th></tr>
+
{{comp table header 1|cols=Price, Launched, Cores, Threads, Frequency, Max Turbo, TDP, L2$, L3$}}
−
{{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}}
 
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Skylake (server)]]
 
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Skylake (server)]]
 
  |?full page name
 
  |?full page name
Line 70: Line 70:
 
  |?l2$ size
 
  |?l2$ size
 
  |?l3$ size
 
  |?l3$ size
−
|?supported memory type
 
−
|?max memory#GiB
 
 
  |format=template
 
  |format=template
 
  |template=proc table 3
 
  |template=proc table 3
−
  |userparam=13
+
  |userparam=11
 
  |mainlabel=-
 
  |mainlabel=-
 
}}
 
}}
 
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Skylake (server)]]}}
 
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Skylake (server)]]}}
 +
</table>
 +
{{comp table end}}
 +
 +
=== 4200-Series (Cascade Lake) ===
 +
{{see also|intel/microarchitectures/cascade lake|intel/cores/cascade lake sp|intel/cores/cascade lake r|l1=Cascade Lake µarch|l2=Cascade Lake SP corename|l3=Cascade Lake R corename}}
 +
Second-generation Xeon Scalable Silver was introduced in early 2019. Those processors are fabricated on an enhanced [[14 nm process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference) as well as support for [[persistent memory]]. All 4200-series Xeon Silver processors support:
 +
 +
* '''Proc:''' [[14 nm process]]
 +
* '''TDP:''' 70 W, 85 W, 100 W
 +
* '''Mem:''' 1 TiB hexa-channel DDR4-2400 ECC memory
 +
* '''I/O:''' 48 PCIe Gen 3.0 lanes
 +
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
 +
* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
 +
 +
All Xeon Silver processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 {{intel|Ultra Path Interconnect}} (UPI) links.
 +
 +
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          This table is generated automatically from the data in the actual articles.
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          If a microprocessor is missing from the list, an appropriate article for it needs to be
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          created and tagged accordingly.
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          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc4 tc5">
 +
{{comp table header|main|9:List of Cascade Lake-based Xeon Silver Processors}}
 +
{{comp table header 1|cols=Price, Launched, Cores, Threads, Frequency, Max Turbo, TDP, L2$, L3$}}
 +
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Cascade Lake]]
 +
|?full page name
 +
|?model number
 +
|?release price
 +
|?first launched
 +
|?core count
 +
|?thread count
 +
|?base frequency#GHz
 +
|?turbo frequency (1 core)#GHz
 +
|?tdp
 +
|?l2$ size
 +
|?l3$ size
 +
|format=template
 +
|template=proc table 3
 +
|valuesep=,
 +
|userparam=11
 +
|mainlabel=-
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Cascade Lake]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}

Latest revision as of 01:57, 2 March 2020

Xeon Silver
xeon silver (2017).png
Xeon Silver Logo
Developer Intel
Manufacturer Intel
Type Microprocessors
Introduction May 4, 2017 (announced)
July 11, 2017 (launch)
Architecture x86 server multiprocessors
ISA x86-64
µarch Skylake
Word size 64 bit
8 octets
16 nibbles
Process 14 nm
0.014 μm
1.4e-5 mm
Technology CMOS
Package FCLGA-3647
Socket LGA-3647
Succession
←
Xeon E7
Xeon E5

Xeon Silver is a family of 64-bit x86 dual-socket multi-core mid-range performance server microprocessors introduced by Intel in 2017.

Overview[edit]

Released in July 2017, the Xeon Silver are the successor to the Xeon E5/E7 families. Xeon Silver is geared toward mid-range workloads dual-socket server. Xeon Silver processors are a set above the Xeon Bronze, offering additional features such as Hyper-Threading and Turbo Boost.

Members[edit]

4100-Series (Skylake)[edit]

See also: Skylake µarch

First-generation Xeon Silver processors were introduced in July 2017. Those chips were fabricated on a enhanced 14nm+ process based on the Skylake microarchitecture which brought a relatively large SoC design change from the prior Xeon families. Those processors were the first to move to a mesh interconnect which introduced a tile-based architecture, bringing the first implementation of AVX-512 along with a rearchitected cache hierarchy designed for server workloads. All of the Silver 4100-series microprocessors feature dual-socket capabilities with up to 12 cores and 24 threads. Additionally, all Xeon Silver processors support:

All Xeon Silver processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 Ultra Path Interconnect (UPI) links.

 List of Skylake-based Xeon Silver Processors
ModelPriceLaunchedCoresThreadsFrequencyMax TurboTDPL2$L3$
4108$ 417.00
€ 375.30
£ 337.77
¥ 43,088.61
11 July 20178161.8 GHz
1,800 MHz
1,800,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
4109T$ 501.00
€ 450.90
£ 405.81
¥ 51,768.33
11 July 20178162 GHz
2,000 MHz
2,000,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
70 W
70,000 mW
0.0939 hp
0.07 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
4110$ 501.00
€ 450.90
£ 405.81
¥ 51,768.33
11 July 20178162.1 GHz
2,100 MHz
2,100,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
4112$ 473.00
€ 425.70
£ 383.13
¥ 48,875.09
11 July 2017482.6 GHz
2,600 MHz
2,600,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
8.25 MiB
8,448 KiB
8,650,752 B
0.00806 GiB
4114$ 694.00
€ 624.60
£ 562.14
¥ 71,711.02
11 July 201710202.2 GHz
2,200 MHz
2,200,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
4114T11 July 201710202.2 GHz
2,200 MHz
2,200,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
4116$ 1,002.00
€ 901.80
£ 811.62
¥ 103,536.66
11 July 201712242.1 GHz
2,100 MHz
2,100,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
4116T11 July 201712242.1 GHz
2,100 MHz
2,100,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
Count: 8

4200-Series (Cascade Lake)[edit]

See also: Cascade Lake µarch, Cascade Lake SP corename, and Cascade Lake R corename

Second-generation Xeon Scalable Silver was introduced in early 2019. Those processors are fabricated on an enhanced 14 nm process based on the Cascade Lake microarchitecture which allows for higher clock speeds and introduced a number of hardware changes against the various speculative execution vulnerabilities. Those processors also introduced new new instructions for the acceleration of machine learning (inference) as well as support for persistent memory. All 4200-series Xeon Silver processors support:

All Xeon Silver processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 Ultra Path Interconnect (UPI) links.

 List of Cascade Lake-based Xeon Silver Processors
ModelPriceLaunchedCoresThreadsFrequencyMax TurboTDPL2$L3$
4208$ 417.00
€ 375.30
£ 337.77
¥ 43,088.61
, $ 428.00
€ 385.20
£ 346.68
¥ 44,225.24
2 April 20198162.1 GHz
2,100 MHz
2,100,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
4209T$ 501.00
€ 450.90
£ 405.81
¥ 51,768.33
2 April 20198162.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
70 W
70,000 mW
0.0939 hp
0.07 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
4210$ 501.00
€ 450.90
£ 405.81
¥ 51,768.33
, $ 511.00
€ 459.90
£ 413.91
¥ 52,801.63
2 April 201910202.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
4210R$ 511.00
€ 459.90
£ 413.91
¥ 52,801.63
, $ 501.00
€ 450.90
£ 405.81
¥ 51,768.33
24 February 202010202.4 GHz
2,400 MHz
2,400,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
100 W
100,000 mW
0.134 hp
0.1 kW
10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
4214$ 694.00
€ 624.60
£ 562.14
¥ 71,711.02
, $ 704.00
€ 633.60
£ 570.24
¥ 72,744.32
2 April 201912242.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
4214R$ 705.00
€ 634.50
£ 571.05
¥ 72,847.65
, $ 694.00
€ 624.60
£ 562.14
¥ 71,711.02
24 February 202012242.4 GHz
2,400 MHz
2,400,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
100 W
100,000 mW
0.134 hp
0.1 kW
12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
4214Y$ 768.00
€ 691.20
£ 622.08
¥ 79,357.44
2 April 201912242.2 GHz
2,200 MHz
2,200,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
4215$ 794.00
€ 714.60
£ 643.14
¥ 82,044.02
2 April 20198162.5 GHz
2,500 MHz
2,500,000 kHz
3.5 GHz
3,500 MHz
3,500,000 kHz
85 W
85,000 mW
0.114 hp
0.085 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
4215R$ 794.00
€ 714.60
£ 643.14
¥ 82,044.02
24 February 20208163.2 GHz
3,200 MHz
3,200,000 kHz
4 GHz
4,000 MHz
4,000,000 kHz
130 W
130,000 mW
0.174 hp
0.13 kW
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
4216$ 1,002.00
€ 901.80
£ 811.62
¥ 103,536.66
, $ 1,012.00
€ 910.80
£ 819.72
¥ 104,569.96
2 April 201916322.1 GHz
2,100 MHz
2,100,000 kHz
3.2 GHz
3,200 MHz
3,200,000 kHz
100 W
100,000 mW
0.134 hp
0.1 kW
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
Count: 10

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_silver&oldid=96310"
Facts about "Xeon Silver - Intel"
RDF feed
designerIntel +
first announcedMay 4, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon silver +
instance ofmicroprocessor family +
instruction set architecturex86-64 +
main designerIntel +
manufacturerIntel +
microarchitectureSkylake +
nameXeon Silver +
packageFCLGA-3647 +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketLGA-3647 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +