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Difference between revisions of "intel/xeon gold/6244"
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{{chip | {{chip | ||
|name=Xeon Gold 6244 | |name=Xeon Gold 6244 | ||
− | |image= | + | |image=cascade lake sp (front).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=6244 | |model number=6244 | ||
+ | |part number=CD8069504194202 | ||
+ | |s-spec=SRF8Z | ||
+ | |s-spec qs=QRAJ | ||
|market=Server | |market=Server | ||
− | |first announced= | + | |first announced=April 2, 2019 |
− | |first launched= | + | |first launched=April 2, 2019 |
+ | |release price (tray)=$2,925.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=6200 |
|locked=Yes | |locked=Yes | ||
|frequency=3,600 MHz | |frequency=3,600 MHz | ||
|turbo frequency1=4,400 MHz | |turbo frequency1=4,400 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
|clock multiplier=36 | |clock multiplier=36 | ||
|isa=x86-64 | |isa=x86-64 | ||
Line 22: | Line 29: | ||
|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
+ | |core model=85 | ||
+ | |core stepping=B0 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 27: | Line 36: | ||
|core count=8 | |core count=8 | ||
|thread count=16 | |thread count=16 | ||
+ | |max memory=1 TiB | ||
|max cpus=4 | |max cpus=4 | ||
+ | |smp interconnect=UPI | ||
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=150 W | |tdp=150 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
− | |tcase max= | + | |tcase max=74 °C |
− | | | + | |package name 1=intel,fclga_3647 |
− | | | + | |predecessor=Xeon Gold 6144 |
− | | | + | |predecessor link=intel/xeon_gold/6144 |
}} | }} | ||
− | '''Xeon Gold 6244''' is a {{arch|64}} [[octa-core]] [[x86]] | + | '''Xeon Gold 6244''' is a {{arch|64}} [[octa-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6244 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.6 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 4.4 GHz. |
+ | |||
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} |
The Xeon Gold 6244 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part. | The Xeon Gold 6244 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part. | ||
{{cache size | {{cache size | ||
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-2933 |
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem=1 TiB |
|controllers=2 | |controllers=2 | ||
|channels=6 | |channels=6 | ||
− | |max bandwidth= | + | |max bandwidth=131.13 GiB/s |
− | |bandwidth schan= | + | |bandwidth schan=21.86 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=43.71 GiB/s |
− | |bandwidth qchan= | + | |bandwidth qchan=87.42 GiB/s |
− | |bandwidth hchan= | + | |bandwidth hchan=131.13 GiB/s |
}} | }} | ||
== Expansions == | == Expansions == | ||
− | {{expansions | + | {{expansions main |
− | | pcie revision | + | | |
− | | pcie lanes | + | {{expansions entry |
− | | pcie config | + | |type=PCIe |
− | | pcie config 2 | + | |pcie revision=3.0 |
− | | pcie config 3 | + | |pcie lanes=48 |
+ | |pcie config=1x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
}} | }} | ||
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|avx512vbmi=No | |avx512vbmi=No | ||
|avx5124fmaps=No | |avx5124fmaps=No | ||
+ | |avx512vnni=Yes | ||
|avx5124vnniw=No | |avx5124vnniw=No | ||
|avx512vpopcntdq=No | |avx512vpopcntdq=No | ||
Line 128: | Line 147: | ||
|clmul=Yes | |clmul=Yes | ||
|f16c=Yes | |f16c=Yes | ||
+ | |bfloat16=No | ||
|tbt1=No | |tbt1=No | ||
|tbt2=Yes | |tbt2=Yes | ||
Line 137: | Line 157: | ||
|fastmem=No | |fastmem=No | ||
|ivmd=Yes | |ivmd=Yes | ||
− | |intelnodecontroller= | + | |intelnodecontroller=No |
|intelnode=Yes | |intelnode=Yes | ||
|kpt=Yes | |kpt=Yes | ||
Line 160: | Line 180: | ||
|securekey=No | |securekey=No | ||
|osguard=No | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=Yes | ||
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 173: | Line 195: | ||
|sensemi=No | |sensemi=No | ||
|xfr=No | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=3,600MHz | ||
+ | |freq_1=4,400MHz | ||
+ | |freq_2=4,400MHz | ||
+ | |freq_3=4,300MHz | ||
+ | |freq_4=4,300MHz | ||
+ | |freq_5=4,300MHz | ||
+ | |freq_6=4,300MHz | ||
+ | |freq_7=4,300MHz | ||
+ | |freq_8=4,300MHz | ||
+ | |freq_avx2_base=3,000MHz | ||
+ | |freq_avx2_1=4,000MHz | ||
+ | |freq_avx2_2=4,000MHz | ||
+ | |freq_avx2_3=3,900MHz | ||
+ | |freq_avx2_4=3,900MHz | ||
+ | |freq_avx2_5=3,900MHz | ||
+ | |freq_avx2_6=3,900MHz | ||
+ | |freq_avx2_7=3,900MHz | ||
+ | |freq_avx2_8=3,900MHz | ||
+ | |freq_avx512_base=2,600MHz | ||
+ | |freq_avx512_1=3,800MHz | ||
+ | |freq_avx512_2=3,800MHz | ||
+ | |freq_avx512_3=3,600MHz | ||
+ | |freq_avx512_4=3,600MHz | ||
+ | |freq_avx512_5=3,500MHz | ||
+ | |freq_avx512_6=3,500MHz | ||
+ | |freq_avx512_7=3,500MHz | ||
+ | |freq_avx512_8=3,500MHz | ||
}} | }} |
Latest revision as of 02:17, 29 December 2019
Edit Values | |
Xeon Gold 6244 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6244 |
Part Number | CD8069504194202 |
S-Spec | SRF8Z QRAJ (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $2,925.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6200 |
Locked | Yes |
Frequency | 3,600 MHz |
Turbo Frequency | 4,400 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 36 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Model | 85 |
Core Stepping | B0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 150 W |
Tcase | 0 °C – 74 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 6244 is a 64-bit octa-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6244 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.6 GHz with a TDP of 150 W and features a turbo boost frequency of up to 4.4 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
The Xeon Gold 6244 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||
---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
Normal | 3,600MHz | 4,400MHz | 4,400MHz | 4,300MHz | 4,300MHz | 4,300MHz | 4,300MHz | 4,300MHz | 4,300MHz |
AVX2 | 3,000MHz | 4,000MHz | 4,000MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz |
AVX512 | 2,600MHz | 3,800MHz | 3,800MHz | 3,600MHz | 3,600MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz |
Facts about "Xeon Gold 6244 - Intel"
full page name | intel/xeon gold/6244 + |
instance of | microprocessor + |
ldate | 1900 + |