From WikiChip
Difference between revisions of "intel/xeon silver/4214y"
< intel‎ | xeon silver

 
(12 intermediate revisions by 3 users not shown)
Line 1: Line 1:
 
{{intel title|Xeon Silver 4214Y}}
 
{{intel title|Xeon Silver 4214Y}}
 
{{chip
 
{{chip
−
|future=Yes
 
 
|name=Xeon Silver 4214Y
 
|name=Xeon Silver 4214Y
−
|image=skylake sp (basic).png
+
|image=cascade lake sp (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=4214Y
 
|model number=4214Y
 +
|part number=CD8069504294401
 +
|s-spec=SRFDG
 +
|s-spec qs=QRHY
 
|market=Server
 
|market=Server
−
|first announced=March 2019
+
|first announced=April 2, 2019
−
|first launched=March 2019
+
|first launched=April 2, 2019
 +
|release price (tray)=$768.00
 
|family=Xeon Silver
 
|family=Xeon Silver
−
|series=4000
+
|series=4200
 
|locked=Yes
 
|locked=Yes
 
|frequency=2,200 MHz
 
|frequency=2,200 MHz
 +
|turbo frequency1=3,200 MHz
 
|clock multiplier=22
 
|clock multiplier=22
 
|isa=x86-64
 
|isa=x86-64
Line 22: Line 26:
 
|core name=Cascade Lake SP
 
|core name=Cascade Lake SP
 
|core family=6
 
|core family=6
 +
|core stepping=L0
 +
|core stepping 2=L1
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
Line 27: Line 33:
 
|core count=12
 
|core count=12
 
|thread count=24
 
|thread count=24
 +
|max memory=1 TiB
 
|max cpus=2
 
|max cpus=2
 +
|smp interconnect=UPI
 +
|smp interconnect links=2
 +
|smp interconnect rate=9.6 GT/s(qs)
 +
|tdp=85 W
 
|tcase min=0 °C
 
|tcase min=0 °C
−
|tcase max=78 °C
+
|tcase max=77 °C
−
|package module 1={{packages/intel/fclga-3647}}
+
|package name 1=intel,fclga_3647
 
}}
 
}}
−
'''Xeon Silver 4214Y''' is a {{arch|64}} [[dodeca-core]] [[x86]] dual-socket mid-range performance server microprocessor set to be introduced by [[Intel]] in early 2019. The Silver 4214Y, which is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3.2 GHz, supports up ? GiB of hexa-channel DDR4-2400 ECC memory.
+
'''Xeon Silver 4214Y''' is a {{arch|64}} [[dodeca-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Silver 4214Y is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 85 W and features a {{intel|turbo boost}} frequency of up to 3.2 GHz.
  
−
 
+
As indicated by the "''Y''" suffix, this model features {{intel|Speed Select Technology}} (SST). It can be configured at 3 different core counts and frequencies - 12 cores, 10 cores, and 8 cores.
−
{{unknown features}}
 
  
  
Line 63: Line 73:
 
|type=DDR4-2400
 
|type=DDR4-2400
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=768 GiB
+
|max mem=1 TiB
 
|controllers=2
 
|controllers=2
 
|channels=6
 
|channels=6
Line 74: Line 84:
  
 
== Expansions ==
 
== Expansions ==
−
{{expansions
+
{{expansions main
−
| pcie revision     = 3.0
+
|
−
| pcie lanes         = 48
+
{{expansions entry
−
| pcie config       = x16
+
|type=PCIe
−
| pcie config 2     = x8
+
|pcie revision=3.0
−
| pcie config 3     = x4
+
|pcie lanes=48
 +
|pcie config=1x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 
}}
 
}}
  
Line 113: Line 127:
 
|avx512vbmi=No
 
|avx512vbmi=No
 
|avx5124fmaps=No
 
|avx5124fmaps=No
 +
|avx512vnni=Yes
 
|avx5124vnniw=No
 
|avx5124vnniw=No
 
|avx512vpopcntdq=No
 
|avx512vpopcntdq=No
Line 128: Line 143:
 
|clmul=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|f16c=Yes
 +
|bfloat16=No
 
|tbt1=No
 
|tbt1=No
 
|tbt2=Yes
 
|tbt2=Yes
Line 137: Line 153:
 
|fastmem=No
 
|fastmem=No
 
|ivmd=Yes
 
|ivmd=Yes
 +
|intelnodecontroller=No
 
|intelnode=Yes
 
|intelnode=Yes
 
|kpt=Yes
 
|kpt=Yes
 
|ptt=Yes
 
|ptt=Yes
 +
|intelrunsure=No
 
|mbe=Yes
 
|mbe=Yes
 
|isrt=No
 
|isrt=No
Line 152: Line 170:
 
|vpro=Yes
 
|vpro=Yes
 
|vtx=Yes
 
|vtx=Yes
−
|vtd=No
+
|vtd=Yes
 
|ept=Yes
 
|ept=Yes
 
|mpx=No
 
|mpx=No
Line 158: Line 176:
 
|securekey=No
 
|securekey=No
 
|osguard=No
 
|osguard=No
 +
|intqat=No
 +
|dlboost=Yes
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
Line 171: Line 191:
 
|sensemi=No
 
|sensemi=No
 
|xfr=No
 
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,200MHz
 +
|freq_1=3,200MHz
 +
|freq_2=3,200MHz
 +
|freq_3=3,000MHz
 +
|freq_4=3,000MHz
 +
|freq_5=2,900MHz
 +
|freq_6=2,900MHz
 +
|freq_7=2,900MHz
 +
|freq_8=2,900MHz
 +
|freq_9=2,700MHz
 +
|freq_10=2,700MHz
 +
|freq_11=2,700MHz
 +
|freq_12=2,700MHz
 +
|freq_avx2_base=1,800MHz
 +
|freq_avx2_1=3,100MHz
 +
|freq_avx2_2=3,100MHz
 +
|freq_avx2_3=2,900MHz
 +
|freq_avx2_4=2,900MHz
 +
|freq_avx2_5=2,800MHz
 +
|freq_avx2_6=2,800MHz
 +
|freq_avx2_7=2,800MHz
 +
|freq_avx2_8=2,800MHz
 +
|freq_avx2_9=2,400MHz
 +
|freq_avx2_10=2,400MHz
 +
|freq_avx2_11=2,400MHz
 +
|freq_avx2_12=2,400MHz
 +
|freq_avx512_base=1,300MHz
 +
|freq_avx512_1=2,000MHz
 +
|freq_avx512_2=2,000MHz
 +
|freq_avx512_3=1,800MHz
 +
|freq_avx512_4=1,800MHz
 +
|freq_avx512_5=1,700MHz
 +
|freq_avx512_6=1,700MHz
 +
|freq_avx512_7=1,700MHz
 +
|freq_avx512_8=1,700MHz
 +
|freq_avx512_9=1,600MHz
 +
|freq_avx512_10=1,600MHz
 +
|freq_avx512_11=1,600MHz
 +
|freq_avx512_12=1,600MHz
 
}}
 
}}

Latest revision as of 11:16, 29 December 2019

Edit Values
Xeon Silver 4214Y
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number4214Y
Part NumberCD8069504294401
S-SpecSRFDG
QRHY (QS)
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$768.00 (tray)
ShopAmazon
General Specs
FamilyXeon Silver
Series4200
LockedYes
Frequency2,200 MHz
Turbo Frequency3,200 MHz (1 core)
Clock multiplier22
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core SteppingL0, L1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores12
Threads24
Max Memory1 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
InterconnectUPI
Interconnect Links2
Interconnect Rate9.6 GT/s(qs)
Electrical
TDP85 W
Tcase0 °C – 77 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Silver 4214Y is a 64-bit dodeca-core x86 mid-range performance server microprocessor introduced by Intel in early 2019. The Silver 4214Y is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 85 W and features a turbo boost frequency of up to 3.2 GHz.

As indicated by the "Y" suffix, this model features Speed Select Technology (SST). It can be configured at 3 different core counts and frequencies - 12 cores, 10 cores, and 8 cores.


Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back
L3$16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
  12x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112
Normal2,200MHz3,200MHz3,200MHz3,000MHz3,000MHz2,900MHz2,900MHz2,900MHz2,900MHz2,700MHz2,700MHz2,700MHz2,700MHz
AVX21,800MHz3,100MHz3,100MHz2,900MHz2,900MHz2,800MHz2,800MHz2,800MHz2,800MHz2,400MHz2,400MHz2,400MHz2,400MHz
AVX5121,300MHz2,000MHz2,000MHz1,800MHz1,800MHz1,700MHz1,700MHz1,700MHz1,700MHz1,600MHz1,600MHz1,600MHz1,600MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_silver/4214y&oldid=95210"
Facts about "Xeon Silver 4214Y - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Silver 4214Y - Intel#pcie +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
chipsetLewisburg +
clock multiplier22 +
core count12 +
core family6 +
core nameCascade Lake SP +
core steppingL0 + and L1 +
designerIntel +
familyXeon Silver +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon silver/4214y +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature350.15 K (77 °C, 170.6 °F, 630.27 °R) +
max cpu count2 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number4214Y +
nameXeon Silver 4214Y +
packageFCLGA-3647 +
part numberCD8069504294401 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 768.00 (€ 691.20, £ 622.08, ¥ 79,357.44) +
release price (tray)$ 768.00 (€ 691.20, £ 622.08, ¥ 79,357.44) +
s-specSRFDG +
s-spec (qs)QRHY +
series4200 +
smp interconnectUPI +
smp interconnect links2 +
smp interconnect rate9.6 GT/s(qs) +
smp max ways2 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2400 +
tdp85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technologyCMOS +
thread count24 +
turbo frequency (1 core)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +