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Difference between revisions of "phytium/feiteng/ft-2000+-64"
< phytium‎ | feiteng

 
(9 intermediate revisions by one other user not shown)
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|first announced=2019
 
|first announced=2019
 
|first launched=2019
 
|first launched=2019
−
|family=FT-2000
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|family=FeiTeng
−
|frequency=2,3000 MHz
+
|series=FT-2000+
 +
|frequency=2,300 MHz
 
|isa=ARMv8.0
 
|isa=ARMv8.0
 
|isa family=ARM
 
|isa family=ARM
 
|microarch=Mars II
 
|microarch=Mars II
 +
|microarch 2=Xiaomi
 
|core name=FTC-662
 
|core name=FTC-662
 
|process=16 nm
 
|process=16 nm
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|die area=370 mm²
 
|die area=370 mm²
 
|word size=64 bit
 
|word size=64 bit
 +
|core count=64
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|thread count=64
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|max cpus=1
 
|tdp=96 W
 
|tdp=96 W
 
|package name 1=phytium,fcbga_3576
 
|package name 1=phytium,fcbga_3576
 
|predecessor=FT-2000/64
 
|predecessor=FT-2000/64
−
|predecessor link=phytium/ft-2000/ft-2000-64
+
|predecessor link=phytium/feiteng/ft-2000-64
 
}}
 
}}
 
'''FT-2000+/64''' is a [[64 core]] [[ARM]] server SoC designed by [[Phytium]] and introduced in [[2019]]. Fabricated on [[TSMC]]'s [[16 nm process]], the chip operates at up 2.3 GHz with a TDP of 96 W. This chip is designed for server, communication, and infrastructure applications.
 
'''FT-2000+/64''' is a [[64 core]] [[ARM]] server SoC designed by [[Phytium]] and introduced in [[2019]]. Fabricated on [[TSMC]]'s [[16 nm process]], the chip operates at up 2.3 GHz with a TDP of 96 W. This chip is designed for server, communication, and infrastructure applications.
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 +
== Cache ==
 +
{{main|phytium/microarchitectures/mars_ii#Memory_Hierarchy|l1=Mars II § Cache}}
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{{cache size
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|l1 cache=4 MiB
 +
|l1i cache=2 MiB
 +
|l1i break=64x32 KiB
 +
|l1d cache=2 MiB
 +
|l1d break=64x32 KiB
 +
|l2 cache=32 MiB
 +
|l2 break=16x2 MiB
 +
}}
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 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-3200
 +
|ecc=Yes
 +
|controllers=8
 +
|channels=8
 +
|max bandwidth=143.1 GiB/s
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|bandwidth schan=17.88 GiB/s
 +
|bandwidth dchan=35.76 GiB/s
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|bandwidth qchan=71.53 GiB/s
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|bandwidth hchan=107.3 GiB/s
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|bandwidth ochan=143.1 GiB/s
 +
}}
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 +
== Expansions ==
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{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 33
 +
| pcie config        = 4x8+x1
 +
| pcie config 2      =
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| sata revision      =
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| sata ports        =
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| usb revision      =
 +
| usb revision 2    =
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| usb ports          =
 +
| usb rate          =
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| uart              =
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| uart ports        =
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| gp io              =
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}}
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== Die ==
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{{main|phytium/microarchitectures/mars_ii#Die|l1=Mars II § Die}}
 +
:[[File:mars ii die.png|400px]]
 +
 +
 +
:[[File:mars ii die (annotated).png|400px]]

Latest revision as of 04:41, 17 July 2023

Edit Values
FT-2000+/64
ft-2000+-64 (front).png
General Info
DesignerPhytium
ManufacturerTSMC
Model NumberFT-2000+/64
MarketServer
Introduction2019 (announced)
2019 (launched)
General Specs
FamilyFeiTeng
SeriesFT-2000+
Frequency2,300 MHz
Microarchitecture
ISAARMv8.0 (ARM)
MicroarchitectureMars II, Xiaomi
Core NameFTC-662
Process16 nm
Transistors6,000,000,000
TechnologyCMOS
Die370 mm²
Word Size64 bit
Cores64
Threads64
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP96 W
Packaging
PackageFCBGA-3576 (BGA)
Dimension61 mm × 61 mm
Contacts3576
ft-2000+-64 (back).png
Succession

FT-2000+/64 is a 64 core ARM server SoC designed by Phytium and introduced in 2019. Fabricated on TSMC's 16 nm process, the chip operates at up 2.3 GHz with a TDP of 96 W. This chip is designed for server, communication, and infrastructure applications.

Cache[edit]

Main article: Mars II § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$4 MiB
4,096 KiB
4,194,304 B
L1I$2 MiB
2,048 KiB
2,097,152 B
64x32 KiB  
L1D$2 MiB
2,048 KiB
2,097,152 B
64x32 KiB  
L2$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  16x2 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3200
Supports ECCYes
Controllers8
Channels8
Max Bandwidth143.1 GiB/s
146,534.4 MiB/s
153.652 GB/s
153,652.455 MB/s
0.14 TiB/s
0.154 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s
Octa 143.1 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes33
Configs4x8+x1


Die[edit]

Main article: Mars II § Die
mars ii die.png


mars ii die (annotated).png
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