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Difference between revisions of "intel/xeon gold/6254"
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{{intel title|Xeon Gold 6254}} | {{intel title|Xeon Gold 6254}} | ||
{{chip | {{chip | ||
− | |||
|name=Xeon Gold 6254 | |name=Xeon Gold 6254 | ||
− | |image= | + | |image=cascade lake sp (front).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=6254 | |model number=6254 | ||
+ | |part number=CD8069504194501 | ||
+ | |s-spec=SRF92 | ||
+ | |s-spec qs=QRAM | ||
|market=Server | |market=Server | ||
− | |first announced= | + | |first announced=April 2, 2019 |
− | |first launched= | + | |first launched=April 2, 2019 |
+ | |release price (tray)=$3,803.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=6200 |
|locked=Yes | |locked=Yes | ||
|frequency=3,100 MHz | |frequency=3,100 MHz | ||
Line 19: | Line 22: | ||
|bus rate=8 GT/s | |bus rate=8 GT/s | ||
|clock multiplier=31 | |clock multiplier=31 | ||
− | |||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
Line 27: | Line 29: | ||
|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
+ | |core model=85 | ||
+ | |core stepping=B0 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 32: | Line 36: | ||
|core count=18 | |core count=18 | ||
|thread count=36 | |thread count=36 | ||
+ | |max memory=1 TiB | ||
|max cpus=4 | |max cpus=4 | ||
− | |package | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
+ | |tdp=200 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=82 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | |predecessor=Xeon Gold 6154 | ||
+ | |predecessor link=intel/xeon_gold/6154 | ||
}} | }} | ||
− | '''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] | + | '''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6254 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 200 W and features a {{intel|turbo boost}} frequency of up to 4 GHz. |
− | |||
− | |||
− | |||
Line 64: | Line 74: | ||
== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-2933 |
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem=1 TiB |
|controllers=2 | |controllers=2 | ||
|channels=6 | |channels=6 | ||
− | |max bandwidth= | + | |max bandwidth=131.13 GiB/s |
− | |bandwidth schan= | + | |bandwidth schan=21.86 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=43.71 GiB/s |
− | |bandwidth qchan= | + | |bandwidth qchan=87.42 GiB/s |
− | |bandwidth hchan= | + | |bandwidth hchan=131.13 GiB/s |
}} | }} | ||
== Expansions == | == Expansions == | ||
− | {{expansions | + | {{expansions main |
− | | pcie revision | + | | |
− | | pcie lanes | + | {{expansions entry |
− | | pcie config | + | |type=PCIe |
− | | pcie config 2 | + | |pcie revision=3.0 |
− | | pcie config 3 | + | |pcie lanes=48 |
+ | |pcie config=1x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
}} | }} | ||
Line 142: | Line 156: | ||
|fastmem=No | |fastmem=No | ||
|ivmd=Yes | |ivmd=Yes | ||
− | |intelnodecontroller= | + | |intelnodecontroller=No |
|intelnode=Yes | |intelnode=Yes | ||
|kpt=Yes | |kpt=Yes | ||
Line 185: | Line 199: | ||
|amdpb2=No | |amdpb2=No | ||
|amdpbod=No | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=3,100MHz | ||
+ | |freq_1=4,000MHz | ||
+ | |freq_2=4,000MHz | ||
+ | |freq_3=3,900MHz | ||
+ | |freq_4=3,900MHz | ||
+ | |freq_5=3,900MHz | ||
+ | |freq_6=3,900MHz | ||
+ | |freq_7=3,900MHz | ||
+ | |freq_8=3,900MHz | ||
+ | |freq_9=3,900MHz | ||
+ | |freq_10=3,900MHz | ||
+ | |freq_11=3,900MHz | ||
+ | |freq_12=3,900MHz | ||
+ | |freq_13=3,900MHz | ||
+ | |freq_14=3,900MHz | ||
+ | |freq_15=3,900MHz | ||
+ | |freq_16=3,900MHz | ||
+ | |freq_17=3,900MHz | ||
+ | |freq_18=3,900MHz | ||
+ | |freq_avx2_base=2,700MHz | ||
+ | |freq_avx2_1=3,800MHz | ||
+ | |freq_avx2_2=3,800MHz | ||
+ | |freq_avx2_3=3,600MHz | ||
+ | |freq_avx2_4=3,600MHz | ||
+ | |freq_avx2_5=3,500MHz | ||
+ | |freq_avx2_6=3,500MHz | ||
+ | |freq_avx2_7=3,500MHz | ||
+ | |freq_avx2_8=3,500MHz | ||
+ | |freq_avx2_9=3,500MHz | ||
+ | |freq_avx2_10=3,500MHz | ||
+ | |freq_avx2_11=3,500MHz | ||
+ | |freq_avx2_12=3,500MHz | ||
+ | |freq_avx2_13=3,500MHz | ||
+ | |freq_avx2_14=3,500MHz | ||
+ | |freq_avx2_15=3,500MHz | ||
+ | |freq_avx2_16=3,500MHz | ||
+ | |freq_avx2_17=3,400MHz | ||
+ | |freq_avx2_18=3,400MHz | ||
+ | |freq_avx512_base=2,200MHz | ||
+ | |freq_avx512_1=3,600MHz | ||
+ | |freq_avx512_2=3,600MHz | ||
+ | |freq_avx512_3=3,400MHz | ||
+ | |freq_avx512_4=3,400MHz | ||
+ | |freq_avx512_5=3,300MHz | ||
+ | |freq_avx512_6=3,300MHz | ||
+ | |freq_avx512_7=3,300MHz | ||
+ | |freq_avx512_8=3,300MHz | ||
+ | |freq_avx512_9=3,300MHz | ||
+ | |freq_avx512_10=3,300MHz | ||
+ | |freq_avx512_11=3,300MHz | ||
+ | |freq_avx512_12=3,300MHz | ||
+ | |freq_avx512_13=3,000MHz | ||
+ | |freq_avx512_14=3,000MHz | ||
+ | |freq_avx512_15=3,000MHz | ||
+ | |freq_avx512_16=3,000MHz | ||
+ | |freq_avx512_17=2,900MHz | ||
+ | |freq_avx512_18=2,900MHz | ||
}} | }} |
Latest revision as of 02:18, 29 December 2019
Edit Values | |
Xeon Gold 6254 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6254 |
Part Number | CD8069504194501 |
S-Spec | SRF92 QRAM (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $3,803.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6200 |
Locked | Yes |
Frequency | 3,100 MHz |
Turbo Frequency | 4,000 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 31 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Model | 85 |
Core Stepping | B0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 18 |
Threads | 36 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 200 W |
Tcase | 0 °C – 82 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 6254 is a 64-bit 18-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6254 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 200 W and features a turbo boost frequency of up to 4 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | ||
Normal | 3,100MHz | 4,000MHz | 4,000MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz | 3,900MHz |
AVX2 | 2,700MHz | 3,800MHz | 3,800MHz | 3,600MHz | 3,600MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,400MHz | 3,400MHz |
AVX512 | 2,200MHz | 3,600MHz | 3,600MHz | 3,400MHz | 3,400MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,000MHz | 3,000MHz | 3,000MHz | 3,000MHz | 2,900MHz | 2,900MHz |
Facts about "Xeon Gold 6254 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6254 - Intel#pcie + |
base frequency | 3,100 MHz (3.1 GHz, 3,100,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 31 + |
core count | 18 + |
core family | 6 + |
core model | 85 + |
core name | Cascade Lake SP + |
core stepping | B0 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/6254 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,152 KiB (1,179,648 B, 1.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
ldate | April 2, 2019 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 355.15 K (82 °C, 179.6 °F, 639.27 °R) + |
max cpu count | 4 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 6254 + |
name | Xeon Gold 6254 + |
package | FCLGA-3647 + |
part number | CD8069504194501 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 3,803.00 (€ 3,422.70, £ 3,080.43, ¥ 392,963.99) + |
release price (tray) | $ 3,803.00 (€ 3,422.70, £ 3,080.43, ¥ 392,963.99) + |
s-spec | SRF92 + |
s-spec (qs) | QRAM + |
series | 6200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2933 + |
tdp | 200 W (200,000 mW, 0.268 hp, 0.2 kW) + |
technology | CMOS + |
thread count | 36 + |
turbo frequency (1 core) | 4,000 MHz (4 GHz, 4,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |