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Difference between revisions of "intel/xeon gold/6254"
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{{intel title|Xeon Gold 6254}}
 
{{intel title|Xeon Gold 6254}}
 
{{chip
 
{{chip
−
|future=Yes
 
 
|name=Xeon Gold 6254
 
|name=Xeon Gold 6254
−
|image=skylake sp (basic).png
+
|image=cascade lake sp (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=6254
 
|model number=6254
 +
|part number=CD8069504194501
 +
|s-spec=SRF92
 +
|s-spec qs=QRAM
 
|market=Server
 
|market=Server
−
|first announced=December, 2018
+
|first announced=April 2, 2019
−
|first launched=December, 2018
+
|first launched=April 2, 2019
 +
|release price (tray)=$3,803.00
 
|family=Xeon Gold
 
|family=Xeon Gold
−
|series=6000
+
|series=6200
 
|locked=Yes
 
|locked=Yes
 
|frequency=3,100 MHz
 
|frequency=3,100 MHz
Line 19: Line 22:
 
|bus rate=8 GT/s
 
|bus rate=8 GT/s
 
|clock multiplier=31
 
|clock multiplier=31
−
|cpuid=0x50655
 
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
Line 27: Line 29:
 
|core name=Cascade Lake SP
 
|core name=Cascade Lake SP
 
|core family=6
 
|core family=6
 +
|core model=85
 +
|core stepping=B0
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
Line 32: Line 36:
 
|core count=18
 
|core count=18
 
|thread count=36
 
|thread count=36
 +
|max memory=1 TiB
 
|max cpus=4
 
|max cpus=4
−
|package module 1={{packages/intel/fclga-3647}}
+
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 +
|tdp=200 W
 +
|tcase min=0 °C
 +
|tcase max=82 °C
 +
|package name 1=intel,fclga_3647
 +
|predecessor=Xeon Gold 6154
 +
|predecessor link=intel/xeon_gold/6154
 
}}
 
}}
−
'''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] multi-socket high performance server microprocessor that was supposed to be released in December of 2018, and has yet to be released because Intel sucks donkey nuts. This chip supports up to 4-way multiprocessing. The Gold 6254, which is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm++ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.1 GHz with a TDP of ? W and a {{intel|turbo boost}} frequency of up to 4 GHz, supports up ? GiB of hexa-channel DDR4-2666 ECC memory.
+
'''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6254 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 200 W and features a {{intel|turbo boost}} frequency of up to 4 GHz.
−
 
 
−
 
 
−
{{unknown features}}
 
  
  
Line 64: Line 74:
 
== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=DDR4-2666
+
|type=DDR4-2933
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=? GiB
+
|max mem=1 TiB
 
|controllers=2
 
|controllers=2
 
|channels=6
 
|channels=6
−
|max bandwidth=119.21 GiB/s
+
|max bandwidth=131.13 GiB/s
−
|bandwidth schan=19.87 GiB/s
+
|bandwidth schan=21.86 GiB/s
−
|bandwidth dchan=39.74 GiB/s
+
|bandwidth dchan=43.71 GiB/s
−
|bandwidth qchan=79.47 GiB/s
+
|bandwidth qchan=87.42 GiB/s
−
|bandwidth hchan=119.21 GiB/s
+
|bandwidth hchan=131.13 GiB/s
 
}}
 
}}
  
 
== Expansions ==
 
== Expansions ==
−
{{expansions
+
{{expansions main
−
| pcie revision     = 3.0
+
|
−
| pcie lanes         = 48
+
{{expansions entry
−
| pcie config       = x16
+
|type=PCIe
−
| pcie config 2     = x8
+
|pcie revision=3.0
−
| pcie config 3     = x4
+
|pcie lanes=48
 +
|pcie config=1x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 
}}
 
}}
  
Line 142: Line 156:
 
|fastmem=No
 
|fastmem=No
 
|ivmd=Yes
 
|ivmd=Yes
−
|intelnodecontroller=Yes
+
|intelnodecontroller=No
 
|intelnode=Yes
 
|intelnode=Yes
 
|kpt=Yes
 
|kpt=Yes
Line 185: Line 199:
 
|amdpb2=No
 
|amdpb2=No
 
|amdpbod=No
 
|amdpbod=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=3,100MHz
 +
|freq_1=4,000MHz
 +
|freq_2=4,000MHz
 +
|freq_3=3,900MHz
 +
|freq_4=3,900MHz
 +
|freq_5=3,900MHz
 +
|freq_6=3,900MHz
 +
|freq_7=3,900MHz
 +
|freq_8=3,900MHz
 +
|freq_9=3,900MHz
 +
|freq_10=3,900MHz
 +
|freq_11=3,900MHz
 +
|freq_12=3,900MHz
 +
|freq_13=3,900MHz
 +
|freq_14=3,900MHz
 +
|freq_15=3,900MHz
 +
|freq_16=3,900MHz
 +
|freq_17=3,900MHz
 +
|freq_18=3,900MHz
 +
|freq_avx2_base=2,700MHz
 +
|freq_avx2_1=3,800MHz
 +
|freq_avx2_2=3,800MHz
 +
|freq_avx2_3=3,600MHz
 +
|freq_avx2_4=3,600MHz
 +
|freq_avx2_5=3,500MHz
 +
|freq_avx2_6=3,500MHz
 +
|freq_avx2_7=3,500MHz
 +
|freq_avx2_8=3,500MHz
 +
|freq_avx2_9=3,500MHz
 +
|freq_avx2_10=3,500MHz
 +
|freq_avx2_11=3,500MHz
 +
|freq_avx2_12=3,500MHz
 +
|freq_avx2_13=3,500MHz
 +
|freq_avx2_14=3,500MHz
 +
|freq_avx2_15=3,500MHz
 +
|freq_avx2_16=3,500MHz
 +
|freq_avx2_17=3,400MHz
 +
|freq_avx2_18=3,400MHz
 +
|freq_avx512_base=2,200MHz
 +
|freq_avx512_1=3,600MHz
 +
|freq_avx512_2=3,600MHz
 +
|freq_avx512_3=3,400MHz
 +
|freq_avx512_4=3,400MHz
 +
|freq_avx512_5=3,300MHz
 +
|freq_avx512_6=3,300MHz
 +
|freq_avx512_7=3,300MHz
 +
|freq_avx512_8=3,300MHz
 +
|freq_avx512_9=3,300MHz
 +
|freq_avx512_10=3,300MHz
 +
|freq_avx512_11=3,300MHz
 +
|freq_avx512_12=3,300MHz
 +
|freq_avx512_13=3,000MHz
 +
|freq_avx512_14=3,000MHz
 +
|freq_avx512_15=3,000MHz
 +
|freq_avx512_16=3,000MHz
 +
|freq_avx512_17=2,900MHz
 +
|freq_avx512_18=2,900MHz
 
}}
 
}}

Latest revision as of 01:18, 29 December 2019

Edit Values
Xeon Gold 6254
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6254
Part NumberCD8069504194501
S-SpecSRF92
QRAM (QS)
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$3,803.00 (tray)
ShopAmazon
General Specs
FamilyXeon Gold
Series6200
LockedYes
Frequency3,100 MHz
Turbo Frequency4,000 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier31
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core Model85
Core SteppingB0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores18
Threads36
Max Memory1 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP200 W
Tcase0 °C – 82 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 6254 is a 64-bit 18-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6254 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 200 W and features a turbo boost frequency of up to 4 GHz.


Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.125 MiB
1,152 KiB
1,179,648 B
L1I$576 KiB
589,824 B
0.563 MiB
18x32 KiB8-way set associative 
L1D$576 KiB
589,824 B
0.563 MiB
18x32 KiB8-way set associativewrite-back
L2$18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
  18x1 MiB16-way set associativewrite-back
L3$24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
  18x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth131.13 GiB/s
134,277.12 MiB/s
140.8 GB/s
140,799.765 MB/s
0.128 TiB/s
0.141 TB/s
Bandwidth
Single 21.86 GiB/s
Double 43.71 GiB/s
Quad 87.42 GiB/s
Hexa 131.13 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112131415161718
Normal3,100MHz4,000MHz4,000MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz
AVX22,700MHz3,800MHz3,800MHz3,600MHz3,600MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,400MHz3,400MHz
AVX5122,200MHz3,600MHz3,600MHz3,400MHz3,400MHz3,300MHz3,300MHz3,300MHz3,300MHz3,300MHz3,300MHz3,300MHz3,300MHz3,000MHz3,000MHz3,000MHz3,000MHz2,900MHz2,900MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6254&oldid=95172"
Facts about "Xeon Gold 6254 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6254 - Intel#io +
base frequency3,100 MHz (3.1 GHz, 3,100,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier31 +
core count18 +
core family6 +
core nameCascade Lake SP +
cpuid0x50655 +
designerIntel +
familyXeon Gold +
first announcedDecember 2018 +
first launchedDecember 2018 +
full page nameintel/xeon gold/6254 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,152 KiB (1,179,648 B, 1.125 MiB) +
l1d$ description8-way set associative +
l1d$ size576 KiB (589,824 B, 0.563 MiB) +
l1i$ description8-way set associative +
l1i$ size576 KiB (589,824 B, 0.563 MiB) +
l2$ description16-way set associative +
l2$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
l3$ description11-way set associative +
l3$ size24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
ldate3000 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max cpu count4 +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureCascade Lake +
model number6254 +
nameXeon Gold 6254 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
series6000 +
smp max ways4 +
supported memory typeDDR4-2666 +
technologyCMOS +
thread count36 +
turbo frequency (1 core)4,000 MHz (4 GHz, 4,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +