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Difference between revisions of "arm holdings/microarchitectures/cortex-a17"
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|manufacturer=TSMC
 
|manufacturer=TSMC
 
|introduction=February 11, 2014
 
|introduction=February 11, 2014
 +
|isa=ARMv7
 
|predecessor=Cortex-A12
 
|predecessor=Cortex-A12
 
|predecessor link=arm_holdings/microarchitectures/cortex-a12
 
|predecessor link=arm_holdings/microarchitectures/cortex-a12
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=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
 
{{empty section}}
 
{{empty section}}
 +
 +
== Licensees ==
 +
Arm named the following companies as licensees.
 +
 +
{{collist
 +
|count = 3
 +
|
 +
* [[VIA]]
 +
* [[MediaTek]]
 +
* [[Realtek]]
 +
* [[Rockchip]]
 +
}}
  
 
== Die ==
 
== Die ==
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* TSMC [[28 nm process]]
 
* TSMC [[28 nm process]]
 
* 89 mm² die size
 
* 89 mm² die size
* Quad-core {{armh|Cortex-A7|l=arch}}
+
* Quad-core {{\\|Cortex-A7}}
 
** ~0.48 mm² per core
 
** ~0.48 mm² per core
* Quad-core {{armh|Cortex-A17|l=arch}} + 2 MiB L2
+
* Quad-core Cortex-A17 + 2 MiB L2
 
** ~1.93 mm² per core
 
** ~1.93 mm² per core
 
** ~3.93 mm² for 2 MiB L2
 
** ~3.93 mm² for 2 MiB L2
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(small quad-core is unlabeled below the big core cluster)
 
(small quad-core is unlabeled below the big core cluster)
 
:[[File:mt6595 die shot.png|600px]]
 
:[[File:mt6595 die shot.png|600px]]
 +
 +
== Bibliography ==
 +
* Mair, Hugh, et al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015.

Latest revision as of 14:25, 31 December 2018

Edit Values
Cortex-A17 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionFebruary 11, 2014
Instructions
ISAARMv7
Succession

Cortex-A17 is the successor to the Cortex-A12, a mid-range performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A17 was designed to be paired with the low-power Cortex-A7 in a big.LITTLE configuration.

Architecture[edit]

Key changes from Cortex-A12[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Block Diagram[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Licensees[edit]

Arm named the following companies as licensees.

Die[edit]

MediaTek MT6595[edit]

  • TSMC 28 nm process
  • 89 mm² die size
  • Quad-core Cortex-A7
    • ~0.48 mm² per core
  • Quad-core Cortex-A17 + 2 MiB L2
    • ~1.93 mm² per core
    • ~3.93 mm² for 2 MiB L2

(small quad-core is unlabeled below the big core cluster)

mt6595 die shot.png

Bibliography[edit]

  • Mair, Hugh, et al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015.
codenameCortex-A17 +
designerARM Holdings +
first launchedFebruary 11, 2014 +
full page namearm holdings/microarchitectures/cortex-a17 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A17 +