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Difference between revisions of "arm holdings/microarchitectures/cortex-a17"
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| Line 6: | Line 6: | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
|introduction=February 11, 2014 | |introduction=February 11, 2014 | ||
| + | |isa=ARMv7 | ||
|predecessor=Cortex-A12 | |predecessor=Cortex-A12 | ||
|predecessor link=arm_holdings/microarchitectures/cortex-a12 | |predecessor link=arm_holdings/microarchitectures/cortex-a12 | ||
| Line 18: | Line 19: | ||
=== Memory Hierarchy === | === Memory Hierarchy === | ||
{{empty section}} | {{empty section}} | ||
| + | |||
| + | == Licensees == | ||
| + | Arm named the following companies as licensees. | ||
| + | |||
| + | {{collist | ||
| + | |count = 3 | ||
| + | | | ||
| + | * [[VIA]] | ||
| + | * [[MediaTek]] | ||
| + | * [[Realtek]] | ||
| + | * [[Rockchip]] | ||
| + | }} | ||
== Die == | == Die == | ||
| Line 23: | Line 36: | ||
* TSMC [[28 nm process]] | * TSMC [[28 nm process]] | ||
* 89 mm² die size | * 89 mm² die size | ||
| − | * Quad-core {{ | + | * Quad-core {{\\|Cortex-A7}} |
** ~0.48 mm² per core | ** ~0.48 mm² per core | ||
| − | * Quad-core | + | * Quad-core Cortex-A17 + 2 MiB L2 |
** ~1.93 mm² per core | ** ~1.93 mm² per core | ||
** ~3.93 mm² for 2 MiB L2 | ** ~3.93 mm² for 2 MiB L2 | ||
| Line 31: | Line 44: | ||
(small quad-core is unlabeled below the big core cluster) | (small quad-core is unlabeled below the big core cluster) | ||
:[[File:mt6595 die shot.png|600px]] | :[[File:mt6595 die shot.png|600px]] | ||
| + | |||
| + | == Bibliography == | ||
| + | * Mair, Hugh, et al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015. | ||
Latest revision as of 14:25, 31 December 2018
| Edit Values | |
| Cortex-A17 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | February 11, 2014 |
| Instructions | |
| ISA | ARMv7 |
| Succession | |
Cortex-A17 is the successor to the Cortex-A12, a mid-range performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A17 was designed to be paired with the low-power Cortex-A7 in a big.LITTLE configuration.
Contents
Architecture[edit]
Key changes from Cortex-A12[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Block Diagram[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Licensees[edit]
Arm named the following companies as licensees.
Die[edit]
MediaTek MT6595[edit]
- TSMC 28 nm process
- 89 mm² die size
- Quad-core Cortex-A7
- ~0.48 mm² per core
- Quad-core Cortex-A17 + 2 MiB L2
- ~1.93 mm² per core
- ~3.93 mm² for 2 MiB L2
(small quad-core is unlabeled below the big core cluster)
Bibliography[edit]
- Mair, Hugh, et al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015.
Facts about "Cortex-A17 - Microarchitectures - ARM"
| codename | Cortex-A17 + |
| designer | ARM Holdings + |
| first launched | February 11, 2014 + |
| full page name | arm holdings/microarchitectures/cortex-a17 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv7 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A17 + |