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'''MT6595''' is a mid-range octa-core [[ARM]] [[LTE]] SoC designed by [[MediaTek]] and introduced in early 2014. This chip, which is fabricated on TSMC's [[28 nm process]], features four [[big core|big]] {{armh|Cortex-A17|l=arch}} cores operating at up to 2.5 GHz and four [[little core|little]] {{armh|Cortex-A7|l=arch}} cores operating at up to 1.7 GHz. The MT6595 incorporates an PowerVR G6200 GPU operating at up to 600 MHz and supports up to dual-channel LPDDR3-1866 memory.
 
'''MT6595''' is a mid-range octa-core [[ARM]] [[LTE]] SoC designed by [[MediaTek]] and introduced in early 2014. This chip, which is fabricated on TSMC's [[28 nm process]], features four [[big core|big]] {{armh|Cortex-A17|l=arch}} cores operating at up to 2.5 GHz and four [[little core|little]] {{armh|Cortex-A7|l=arch}} cores operating at up to 1.7 GHz. The MT6595 incorporates an PowerVR G6200 GPU operating at up to 600 MHz and supports up to dual-channel LPDDR3-1866 memory.
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 +
== Cache ==
 +
{{main|arm_holdings/microarchitectures/cortex-a7#Memory_Hierarchy|l1=Cortex-A7 § Cache}}
 +
 +
{{armh|Cortex-A7|l=arch}} Cluster:
 +
 +
{{cache size
 +
|l2 cache=512 KiB
 +
|l2 break=1x512 KiB
 +
}}
 +
 +
{{armh|Cortex-A17|l=arch}} Cluster:
 +
 +
{{cache size
 +
|l2 cache=2 MiB
 +
|l2 break=1x2 MiB
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR3-1866
 +
|ecc=No
 +
|controllers=1
 +
|channels=2
 +
}}
  
 
== Graphics ==
 
== Graphics ==
Line 88: Line 113:
 
(small quad-core is unlabeled below the big core cluster)
 
(small quad-core is unlabeled below the big core cluster)
 
:[[File:mt6595 die shot.png|600px]]
 
:[[File:mt6595 die shot.png|600px]]
 +
 +
== Bibliography ==
 +
* Mair, Hugh, et al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015.

Latest revision as of 12:44, 29 December 2018

Edit Values
MT6595
General Info
DesignerMediaTek,
ARM Holdings
ManufacturerTSMC
Model NumberMT6595
Part NumberMT6595
MarketMobile
IntroductionFebruray 11, 2014 (announced)
Februray 11, 2014 (launched)
General Specs
FamilyMT65xx
Frequency2,500 MHz, 1,700 MHz
Microarchitecture
ISAARMv7 (ARM)
MicroarchitectureCortex-A17, Cortex-A7
Core NameCortex-A17, Cortex-A7
Process28 nm
TechnologyCMOS
Die89 mm²
Word Size64 bit
Cores8
Threads8
Multiprocessing
Max SMP1-Way (Uniprocessor)

MT6595 is a mid-range octa-core ARM LTE SoC designed by MediaTek and introduced in early 2014. This chip, which is fabricated on TSMC's 28 nm process, features four big Cortex-A17 cores operating at up to 2.5 GHz and four little Cortex-A7 cores operating at up to 1.7 GHz. The MT6595 incorporates an PowerVR G6200 GPU operating at up to 600 MHz and supports up to dual-channel LPDDR3-1866 memory.

Cache[edit]

Main article: Cortex-A7 § Cache


Cortex-A7 Cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB  

Cortex-A17 Cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866
Supports ECCNo
Controllers1
Channels2

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR G6200
DesignerImagination Technologies
Frequency600 MHz
0.6 GHz
600,000 KHz
OutputDSI
Max Resolution
DSI2560x1600
Standards
Direct3D10.0
OpenGL3.2
OpenCL1.2
OpenGL ES3.1
Vulkan1.0
  • Encoding H.265
  • Playback H.264, H.265 / HEVC, VP-9

Camera[edit]

  • Image signal processor
    • 20 Mpixel

Connectivity[edit]

  • UE Cat-4
  • EDGE, FDD / TDD LTE, HSPA +, TD-SCDMA
  • Bluetooth
  • Wi-Fi
    • a/b/g/n/ac

Location[edit]

  • GNSS
    • GPS, Glonass, Beidou, Galileo

Utilizing devices[edit]

  • Gionee P7 Max
  • InFocus M530
  • Zopo ZP999
  • Meizu MX4

This list is incomplete; you can help by expanding it.

Die[edit]

(small quad-core is unlabeled below the big core cluster)

mt6595 die shot.png

Bibliography[edit]

  • Mair, Hugh, et al. "23.3 A highly integrated smartphone SoC featuring a 2.5 GHz octa-core CPU with advanced high-performance and low-power techniques." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015.
Retrieved from "https://en.wikichip.org/w/index.php?title=mediatek/mt65xx/mt6595&oldid=85333"
Facts about "MT6595 - MediaTek"
RDF feed
base frequency2,500 MHz (2.5 GHz, 2,500,000 kHz) + and 1,700 MHz (1.7 GHz, 1,700,000 kHz) +
core count8 +
core nameCortex-A17 + and Cortex-A7 +
designerMediaTek + and ARM Holdings +
die area89 mm² (0.138 in², 0.89 cm², 89,000,000 µm²) +
familyMT65xx +
first announcedNovember 2014 +
first launchedNovember 2014 +
full page namemediatek/mt65xx/mt6595 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR G6200 +
integrated gpu base frequency600 MHz (0.6 GHz, 600,000 KHz) +
integrated gpu designerImagination Technologies +
isaARMv7 +
isa familyARM +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + and 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateNovember 2014 +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory channels2 +
microarchitectureCortex-A17 + and Cortex-A7 +
model numberMT6595 +
nameMT6595 +
part numberMT6595 +
process28 nm (0.028 μm, 2.8e-5 mm) +
smp max ways1 +
supported memory typeLPDDR3-1866 +
technologyCMOS +
thread count8 +
used byGionee P7 Max +, InFocus M530 +, Zopo ZP999 + and Meizu MX4 +
word size64 bit (8 octets, 16 nibbles) +