Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "arm holdings/microarchitectures/cortex-a9"
(Falcon codename added) |
|||
| (10 intermediate revisions by 2 users not shown) | |||
| Line 7: | Line 7: | ||
|introduction=October 3, 2007 | |introduction=October 3, 2007 | ||
|process=40 nm | |process=40 nm | ||
| + | |isa=ARMv7 | ||
|predecessor=Cortex-A8 | |predecessor=Cortex-A8 | ||
|predecessor link=arm_holdings/microarchitectures/cortex-a8 | |predecessor link=arm_holdings/microarchitectures/cortex-a8 | ||
| Line 18: | Line 19: | ||
|successor 4 link=arm_holdings/microarchitectures/cortex-a5 | |successor 4 link=arm_holdings/microarchitectures/cortex-a5 | ||
}} | }} | ||
| − | '''Cortex-A9''' is the successor to the {{armh|Cortex-A8|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. | + | '''Cortex-A9''' (codename '''Falcon''') is the successor to the {{armh|Cortex-A8|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. |
| − | The Cortex-A9 was later succeeded by | + | The Cortex-A9 was later succeeded by four independent lines - high-performance ({{\\|Cortex-A15|A15}}), mainstream performance ({{\\|Cortex-A12|A12}}), high efficiency ({{\\|Cortex-A7|A7}}), and ultra-low power ({{\\|Cortex-A5|A5}}). |
| + | |||
| + | == Compiler support == | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Compiler !! Arch-Specific || Arch-Favorable | ||
| + | |- | ||
| + | | [[Arm Compiler]] || <code>-mcpu=cortex-a9</code> || <code>-mtune=cortex-a9</code> | ||
| + | |- | ||
| + | | [[GCC]] || <code>-mcpu=cortex-a9</code> || <code>-mtune=cortex-a9</code> | ||
| + | |- | ||
| + | | [[LLVM]] || <code>-mcpu=cortex-a9</code> || <code>-mtune=cortex-a9</code> | ||
| + | |} | ||
| + | |||
| + | One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because [[NEON]], under [[ARMv7]], is not fully [[IEEE 754]]-compliant. It's possible to use <code>-funsafe-math-optimizations</code> to circumvent that behavior. | ||
| + | |||
| + | == Architecture == | ||
| + | === Key changes from {{\\|Cortex-A8}} === | ||
| + | * Fully synthesizable RTL (prior designs were hand/automated layout) | ||
| + | * [[40 nm process]] (from [[65 nm]]) | ||
| + | * New [[out-of-order]] pipeline (from [[in-order]]) | ||
| + | ** Shorter pipeline (9-12 stages, down from 13) | ||
| + | * 2x frequency (2 GHz, up from 1 GHz) | ||
| + | * NEON | ||
| + | ** Added [[Half precision]] support | ||
| + | {{expand list}} | ||
| + | |||
| + | == Licensees == | ||
| + | Arm named the following companies as licensees. | ||
| + | |||
| + | {{collist | ||
| + | |count = 3 | ||
| + | | | ||
| + | * [[Broadcom]] | ||
| + | * [[Freescale]] | ||
| + | * [[NEC]] | ||
| + | * [[nVIDIA]] | ||
| + | * [[STMicroelectronics]] | ||
| + | * [[Texas Instruments]] | ||
| + | * [[Toshiba]] | ||
| + | * [[Mindspeed Technologies]] | ||
| + | * [[ZiiLABS]] | ||
| + | * [[Open-Silicon]] | ||
| + | * [[eSilicon]] | ||
| + | * [[Altera]] | ||
| + | * [[Xilinx]] | ||
| + | }} | ||
Latest revision as of 11:27, 28 July 2019
| Edit Values | |
| Cortex-A9 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | October 3, 2007 |
| Process | 40 nm |
| Instructions | |
| ISA | ARMv7 |
| Succession | |
Cortex-A9 (codename Falcon) is the successor to the Cortex-A8, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
The Cortex-A9 was later succeeded by four independent lines - high-performance (A15), mainstream performance (A12), high efficiency (A7), and ultra-low power (A5).
Compiler support[edit]
| Compiler | Arch-Specific | Arch-Favorable |
|---|---|---|
| Arm Compiler | -mcpu=cortex-a9 |
-mtune=cortex-a9
|
| GCC | -mcpu=cortex-a9 |
-mtune=cortex-a9
|
| LLVM | -mcpu=cortex-a9 |
-mtune=cortex-a9
|
One can specify NEON support using the -mfpu=neon option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because NEON, under ARMv7, is not fully IEEE 754-compliant. It's possible to use -funsafe-math-optimizations to circumvent that behavior.
Architecture[edit]
Key changes from Cortex-A8[edit]
- Fully synthesizable RTL (prior designs were hand/automated layout)
- 40 nm process (from 65 nm)
- New out-of-order pipeline (from in-order)
- Shorter pipeline (9-12 stages, down from 13)
- 2x frequency (2 GHz, up from 1 GHz)
- NEON
- Added Half precision support
This list is incomplete; you can help by expanding it.
Licensees[edit]
Arm named the following companies as licensees.
Facts about "Cortex-A9 - Microarchitectures - ARM"
| codename | Cortex-A9 + |
| designer | ARM Holdings + |
| first launched | October 3, 2007 + |
| full page name | arm holdings/microarchitectures/cortex-a9 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv7 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A9 + |
| process | 40 nm (0.04 μm, 4.0e-5 mm) + |