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|manufacturer=TSMC
 
|manufacturer=TSMC
 
|introduction=October 3, 2007
 
|introduction=October 3, 2007
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|process=40 nm
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|isa=ARMv7
 
|predecessor=Cortex-A8
 
|predecessor=Cortex-A8
 
|predecessor link=arm_holdings/microarchitectures/cortex-a8
 
|predecessor link=arm_holdings/microarchitectures/cortex-a8
 
|successor=Cortex-A15
 
|successor=Cortex-A15
 
|successor link=arm_holdings/microarchitectures/cortex-a15
 
|successor link=arm_holdings/microarchitectures/cortex-a15
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|successor 2=Cortex-A7
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|successor 2 link=arm_holdings/microarchitectures/cortex-a7
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|successor 3=Cortex-A12
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|successor 3 link=arm_holdings/microarchitectures/cortex-a12
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|successor 4=Cortex-A5
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|successor 4 link=arm_holdings/microarchitectures/cortex-a5
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}}
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'''Cortex-A9''' (codename '''Falcon''') is the successor to the {{armh|Cortex-A8|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
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The Cortex-A9 was later succeeded by four independent lines - high-performance ({{\\|Cortex-A15|A15}}), mainstream performance ({{\\|Cortex-A12|A12}}), high efficiency ({{\\|Cortex-A7|A7}}), and ultra-low power ({{\\|Cortex-A5|A5}}).
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== Compiler support ==
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{| class="wikitable"
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|-
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! Compiler !! Arch-Specific || Arch-Favorable
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|-
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| [[Arm Compiler]] || <code>-mcpu=cortex-a9</code> || <code>-mtune=cortex-a9</code>
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|-
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| [[GCC]] || <code>-mcpu=cortex-a9</code> || <code>-mtune=cortex-a9</code>
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|-
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| [[LLVM]] || <code>-mcpu=cortex-a9</code> || <code>-mtune=cortex-a9</code>
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|}
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One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because [[NEON]], under [[ARMv7]], is not fully [[IEEE 754]]-compliant. It's possible to use <code>-funsafe-math-optimizations</code> to circumvent that behavior.
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== Architecture ==
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=== Key changes from {{\\|Cortex-A8}} ===
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* Fully synthesizable RTL (prior designs were hand/automated layout)
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* [[40 nm process]] (from [[65 nm]])
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* New [[out-of-order]] pipeline (from [[in-order]])
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** Shorter pipeline (9-12 stages, down from 13)
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* 2x frequency (2 GHz, up from 1 GHz)
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* NEON
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** Added [[Half precision]] support
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{{expand list}}
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== Licensees ==
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Arm named the following companies as licensees.
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{{collist
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|count = 3
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|
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* [[Broadcom]]
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* [[Freescale]]
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* [[NEC]]
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* [[nVIDIA]]
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* [[STMicroelectronics]]
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* [[Texas Instruments]]
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* [[Toshiba]]
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* [[Mindspeed Technologies]]
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* [[ZiiLABS]]
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* [[Open-Silicon]]
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* [[eSilicon]]
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* [[Altera]]
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* [[Xilinx]]
 
}}
 
}}
'''Cortex-A9''' is the successor to the {{armh|Cortex-A8|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
 

Latest revision as of 11:27, 28 July 2019

Edit Values
Cortex-A9 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
IntroductionOctober 3, 2007
Process40 nm
Instructions
ISAARMv7
Succession

Cortex-A9 (codename Falcon) is the successor to the Cortex-A8, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

The Cortex-A9 was later succeeded by four independent lines - high-performance (A15), mainstream performance (A12), high efficiency (A7), and ultra-low power (A5).

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
Arm Compiler -mcpu=cortex-a9 -mtune=cortex-a9
GCC -mcpu=cortex-a9 -mtune=cortex-a9
LLVM -mcpu=cortex-a9 -mtune=cortex-a9

One can specify NEON support using the -mfpu=neon option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because NEON, under ARMv7, is not fully IEEE 754-compliant. It's possible to use -funsafe-math-optimizations to circumvent that behavior.

Architecture[edit]

Key changes from Cortex-A8[edit]

This list is incomplete; you can help by expanding it.

Licensees[edit]

Arm named the following companies as licensees.

codenameCortex-A9 +
designerARM Holdings +
first launchedOctober 3, 2007 +
full page namearm holdings/microarchitectures/cortex-a9 +
instance ofmicroarchitecture +
instruction set architectureARMv7 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-A9 +
process40 nm (0.04 μm, 4.0e-5 mm) +