From WikiChip
Difference between revisions of "amd/epyc/7261"
< amd‎ | epyc

m
(Replaced package module by package name.)
 
(2 intermediate revisions by one other user not shown)
Line 43: Line 43:
 
|tdp=155 W
 
|tdp=155 W
 
|tdp 2=170 W
 
|tdp 2=170 W
−
|package module 1={{packages/amd/socket sp3}}
+
|package name 1=amd,socket_sp3
 
}}
 
}}
−
'''EPYC 7261''' is a dual-socket {{arch|64}} [[octa-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid-[[2017]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7261 has a base frequency of 2.5 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 170 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket. The TDP is slightly lower at 155 W if DDR4-2400 is used instead.
+
'''EPYC 7261''' is a dual-socket {{arch|64}} [[octa-core]] [[x86]] enterprise server microprocessor introduced by [[AMD]] in mid [[2018]]. This processor is based on the {{amd|Zen|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. The 7261 has a base frequency of 2.5 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 170 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket. The TDP is slightly lower at 155 W if DDR4-2400 is used instead.
  
  
Line 89: Line 89:
  
 
== Expansions ==
 
== Expansions ==
−
The EPYC 7351P has 128 Gen 3 PCIe lanes.
+
The EPYC 7261 has 128 Gen 3 PCIe lanes.
 
{{expansions
 
{{expansions
 
| pcie revision      = 3.0
 
| pcie revision      = 3.0

Latest revision as of 11:36, 18 March 2023

Edit Values
EPYC 7261
General Info
DesignerAMD
ManufacturerGlobalFoundries
Model Number7261
Part NumberPS7261BEV8RAF
MarketServer
IntroductionJune 14, 2018 (announced)
June 14, 2018 (launched)
ShopAmazon
General Specs
FamilyEPYC
Series7000
LockedNo
Frequency2,500 MHz
Turbo Frequency2,900 MHz (1 core),
2,900 MHz (2 cores),
2,900 MHz (3 cores),
2,900 MHz (4 cores),
2,900 MHz (5 cores),
2,900 MHz (6 cores),
2,900 MHz (7 cores),
2,900 MHz (8 cores)
Clock multiplier25
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen
Core NameNaples
Core Family23
Core Model1
Core SteppingB2
Process14 nm
Transistors19,200,000,000
TechnologyCMOS
Die213 mm²
MCPYes (4 dies)
Word Size64 bit
Cores8
Threads16
Max Memory2 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP155 W, 170 W
Packaging
PackageSP3, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm × 58.5 mm × 6.26 mm
Pitch0.87 mm × 1 mm
Contacts4094
SocketSP3, LGA-4094

EPYC 7261 is a dual-socket 64-bit octa-core x86 enterprise server microprocessor introduced by AMD in mid 2018. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7261 has a base frequency of 2.5 GHz with a turbo frequency of 2.9 GHz for all cores. This chip has a TDP of 170 W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket. The TDP is slightly lower at 155 W if DDR4-2400 is used instead.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache[edit]

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$512 KiB
524,288 B
0.5 MiB
8x64 KiB4-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  8x512 KiB8-way set associativewrite-back
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  8x8 MiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666, DDR4-2400
Supports ECCYes
Max Mem2 TiB
Controllers8
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

In a dual-socket configuration, the maximum supported memory doubles to 4 TiB along with the maximum theoretical bandwidth of 286.2 GiB/s.

Expansions[edit]

The EPYC 7261 has 128 Gen 3 PCIe lanes.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes128
Configs8x16, 32x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SMESecure Memory Encryption
TSMETransparent SME
SEVSecure Encrypted Virtualization
SenseMISenseMI Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7261&oldid=101309"
Facts about "EPYC 7261 - AMD"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC 7261 - AMD#io +
base frequency2,500 MHz (2.5 GHz, 2,500,000 kHz) +
clock multiplier25 +
core count8 +
core family23 +
core model1 +
core nameNaples +
core steppingB2 +
designerAMD +
die area213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count4 +
familyEPYC +
first announcedJune 14, 2018 +
first launchedJune 14, 2018 +
full page nameamd/epyc/7261 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multiplierfalse +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description4-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description16-way set associative +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldateJune 14, 2018 +
manufacturerGlobalFoundries +
market segmentServer +
max cpu count2 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
max memory bandwidth158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) +
max memory channels8 +
max pcie lanes128 +
microarchitectureZen +
model number7261 +
nameEPYC 7261 +
part numberPS7261BEV8RAF +
process14 nm (0.014 μm, 1.4e-5 mm) +
series7000 +
smp max ways2 +
supported memory typeDDR4-2666 + and DDR4-2400 +
tdp155 W (155,000 mW, 0.208 hp, 0.155 kW) + and 170 W (170,000 mW, 0.228 hp, 0.17 kW) +
technologyCMOS +
thread count16 +
transistor count19,200,000,000 +
turbo frequency (1 core)2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (2 cores)2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (3 cores)2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (4 cores)2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (5 cores)2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (6 cores)2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (7 cores)2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (8 cores)2,900 MHz (2.9 GHz, 2,900,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +