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Difference between revisions of "hisilicon/kunpeng/hi1612"
< hisilicon‎ | kunpeng

 
(13 intermediate revisions by the same user not shown)
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|designer 2=ARM Holdings
 
|designer 2=ARM Holdings
 
|manufacturer=TSMC
 
|manufacturer=TSMC
−
|model number=Hi1610
+
|model number=Hi1612
 
|market=Server
 
|market=Server
 
|first announced=June 4, 2016
 
|first announced=June 4, 2016
Line 16: Line 16:
 
|microarch=Cortex-A57
 
|microarch=Cortex-A57
 
|core name=Cortex-A57
 
|core name=Cortex-A57
 +
|process=16 nm
 
|technology=CMOS
 
|technology=CMOS
 
|word size=64 bit
 
|word size=64 bit
 
|core count=32
 
|core count=32
 
|thread count=32
 
|thread count=32
−
|max cpus=1
+
|max cpus=2
 +
|max memory=256 GiB
 
}}
 
}}
−
'''Hi1612''' is a [[dotriaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in mid-2016. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 32 {{armh|Cortex-A57}} cores operating at 2.1 GHz. The 1612 supports up to 256 GiB of DDR4-2133 memory.
+
'''Hi1612''' is a [[dotriaconta-core]] {{arch|64}} [[ARM]] server microprocessor introduced by HiSilicon in mid-2016. Fabricated by [[TSMC]] on a [[16 nm process]], this chip incorporates 32 {{armh|Cortex-A57}} cores operating at 2.1 GHz. The 1612 supports up to 256 GiB of quad-channel DDR4-2133 memory.
  
 
== Cache ==
 
== Cache ==
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|l1i break=32x48 KiB
 
|l1i break=32x48 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1d cache=1 KiB
+
|l1d cache=1 MiB
 
|l1d break=32x32 KiB
 
|l1d break=32x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
Line 41: Line 43:
 
|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
 
}}
 
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2133
 +
|ecc=Yes
 +
|max mem=256 GiB
 +
|controllers=1
 +
|channels=4
 +
|width=64 bit
 +
|max bandwidth=63.58 GiB/s
 +
|bandwidth schan=15.89 GiB/s
 +
|bandwidth dchan=31.79 GiB/s
 +
|bandwidth qchan=63.58 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=16
 +
|pcie config=2x8
 +
}}
 +
}}
 +
== Features ==
 +
{{arm features
 +
|thumb=No
 +
|thumb2=No
 +
|thumbee=No
 +
|vfpv1=No
 +
|vfpv2=No
 +
|vfpv3=No
 +
|vfpv3-d16=No
 +
|vfpv3-f16=No
 +
|vfpv4=No
 +
|vfpv4-d16=No
 +
|vfpv5=No
 +
|neon=Yes
 +
|trustzone=No
 +
|jazelle=No
 +
|wmmx=No
 +
|wmmx2=No
 +
|pmuv3=No
 +
|crc32=Yes
 +
|crypto=No
 +
|fp=No
 +
|fp16=No
 +
|profile=No
 +
|ras=No
 +
|simd=No
 +
|rdm=No
 +
}}
 +
 +
== Utilizing devices ==
 +
* [[used by::HiSilicon D03]]
 +
* [[used by::Huawei Taishan 2180]]
 +
 +
{{expand list}}

Latest revision as of 19:49, 5 May 2019

Edit Values
Hi1612
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model NumberHi1612
MarketServer
IntroductionJune 4, 2016 (announced)
June 4, 2016 (launched)
General Specs
FamilyHi16xx
Frequency2,100 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A57
Core NameCortex-A57
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores32
Threads32
Max Memory256 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)

Hi1612 is a dotriaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in mid-2016. Fabricated by TSMC on a 16 nm process, this chip incorporates 32 Cortex-A57 cores operating at 2.1 GHz. The 1612 supports up to 256 GiB of quad-channel DDR4-2133 memory.

Cache[edit]

Main article: Cortex-A57 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2.5 MiB
2,560 KiB
2,621,440 B
L1I$1.5 MiB
1,536 KiB
1,572,864 B
32x48 KiB8-way set associative 
L1D$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB8-way set associative 
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  32x256 KiB8-way set associative 
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  32x1 MiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem256 GiB
Controllers1
Channels4
Width64 bit
Max Bandwidth63.58 GiB/s
65,105.92 MiB/s
68.269 GB/s
68,268.505 MB/s
0.0621 TiB/s
0.0683 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s
Quad 63.58 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 16
Configuration: 2x8

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension

Utilizing devices[edit]

  • HiSilicon D03
  • Huawei Taishan 2180

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kunpeng/hi1612&oldid=89639"
Facts about "Hi1612 - HiSilicon"
RDF feed
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
core count32 +
core nameCortex-A57 +
designerHiSilicon + and ARM Holdings +
familyHi16xx +
first announcedJune 4, 2016 +
first launchedJune 4, 2016 +
full page namehisilicon/kunpeng/hi1612 +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size2,560 KiB (2,621,440 B, 2.5 MiB) +
l1d$ description8-way set associative +
l1d$ size1 KiB (1,024 B, 9.765625e-4 MiB) +
l1i$ description8-way set associative +
l1i$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateJune 4, 2016 +
manufacturerTSMC +
market segmentServer +
max cpu count1 +
microarchitectureCortex-A57 +
model numberHi1610 +
nameHi1612 +
smp max ways1 +
technologyCMOS +
thread count32 +
word size64 bit (8 octets, 16 nibbles) +