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'''ThunderX2 CN9960''' is a {{arch|64}} [[hexadeca-core]] high-performance [[ARM]] server microprocessor introduced by [[Cavium]] in mid-[[2018]]. The microprocessor, which is based on the {{cavium|Vulcan|l=arch}} microarchitecture, is fabricated on [[TSMC]]'s [[16 nm process]]. Depending on the exact SKU, the CN9960 operates between 1.6 GHz and 2.2 GHz and supports up to quad-channel DDR4-2666 memory.
 
'''ThunderX2 CN9960''' is a {{arch|64}} [[hexadeca-core]] high-performance [[ARM]] server microprocessor introduced by [[Cavium]] in mid-[[2018]]. The microprocessor, which is based on the {{cavium|Vulcan|l=arch}} microarchitecture, is fabricated on [[TSMC]]'s [[16 nm process]]. Depending on the exact SKU, the CN9960 operates between 1.6 GHz and 2.2 GHz and supports up to quad-channel DDR4-2666 memory.
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== Cache ==
 +
{{main|cavium/microarchitectures/vulcan#Memory_Hierarchy|l1=Vulcan § Cache}}
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{{cache size
 +
|l1 cache=1 MiB
 +
|l1i cache=512 KiB
 +
|l1i break=16x32 KiB
 +
|l1i desc=8-way set associative
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|l1d cache=512 KiB
 +
|l1d break=16x32 KiB
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|l1d desc=8-way set associative
 +
|l2 cache=4 MiB
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|l2 break=16x256 KiB
 +
|l2 desc=8-way set associative
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|l3 cache=16 MiB
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|l3 break=16x1 MiB
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR4-2666
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|ecc=Yes
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|max mem=2 TiB
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|controllers=2
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|channels=4
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|max bandwidth=79.47 GiB/s
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|bandwidth schan=19.87 GiB/s
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|bandwidth dchan=39.74 GiB/s
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|bandwidth qchan=79.47 GiB/s
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}}
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== Expansions ==
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{{expansions main
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|
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{{expansions entry
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|type=PCIe
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|pcie revision=3.0
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|pcie lanes=48
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|pcie config=x16
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|pcie config 2=x8
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|pcie config 3=x4
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|pcie config 4=x1
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}}
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{{expansions entry
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|type=SATA
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|sata revision=3
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|sata ports=2
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}}
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{{expansions entry
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|type=USB
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|usb revision=3
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|usb ports=2
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}}
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}}
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== Features ==
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{{arm features
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|thumb=No
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|thumb2=No
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|thumbee=No
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|vfpv1=No
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|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=No
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|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
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|trustzone=Yes
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|jazelle=No
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|wmmx=No
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|wmmx2=No
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|pmuv3=Yes
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|crc32=Yes
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|crypto=Yes
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|fp=Yes
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|fp16=No
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|profile=No
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|ras=No
 +
|simd=Yes
 +
|rdm=No
 +
}}

Latest revision as of 23:11, 3 December 2018

Edit Values
ThunderX2 CN9960
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN9960
Part NumberCN9960-2200LG4077-Y21-G,
CN9960-2000LG4077-Y21-G,
CN9960-1800LG4077-Y21-G,
CN9960-1600LG4077-Y21-G
MarketServer
IntroductionMay 7, 2018 (announced)
May 7, 2018 (launched)
General Specs
FamilyThunderX2
Frequency1,600 MHz, 1,800 MHz, 2,000 MHz, 2,200 MHz
Microarchitecture
ISAARMv8.1 (ARM)
MicroarchitectureVulcan
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores16
Threads64
Max Memory2 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Packaging
PackageFCLGA-4077 (LGA)
Contacts4077

ThunderX2 CN9960 is a 64-bit hexadeca-core high-performance ARM server microprocessor introduced by Cavium in mid-2018. The microprocessor, which is based on the Vulcan microarchitecture, is fabricated on TSMC's 16 nm process. Depending on the exact SKU, the CN9960 operates between 1.6 GHz and 2.2 GHz and supports up to quad-channel DDR4-2666 memory.

Cache[edit]

Main article: Vulcan § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1 MiB
1,024 KiB
1,048,576 B
L1I$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associative 
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  16x256 KiB8-way set associative 
L3$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  16x1 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem2 TiB
Controllers2
Channels4
Max Bandwidth79.47 GiB/s
81,377.28 MiB/s
85.33 GB/s
85,330.263 MB/s
0.0776 TiB/s
0.0853 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: x16, x8, x4, x1
SATARevision: 3
Max Ports: 2
USBRevision: 3
Max Ports: 2


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions
PMUv3ARMv8 PMUv3 Performance Monitors Extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension
SIMDAdvanced SIMD extension
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/thunderx2/cn9960&oldid=84611"
Facts about "ThunderX2 CN9960 - Cavium"
RDF feed
base frequency1,600 MHz (1.6 GHz, 1,600,000 kHz) +, 1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,000 MHz (2 GHz, 2,000,000 kHz) + and 2,200 MHz (2.2 GHz, 2,200,000 kHz) +
core count16 +
designerCavium +
familyThunderX2 +
first announcedMay 7, 2018 +
first launchedMay 7, 2018 +
full page namecavium/thunderx2/cn9960 +
instance ofmicroprocessor +
isaARMv8.1 +
isa familyARM +
l1$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description8-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
ldateMay 7, 2018 +
manufacturerTSMC +
market segmentServer +
max cpu count2 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
microarchitectureVulcan +
model numberCN9960 +
nameThunderX2 CN9960 +
packageFCLGA-4077 +
part numberCN9960-2200LG4077-Y21-G +, CN9960-2000LG4077-Y21-G +, CN9960-1800LG4077-Y21-G + and CN9960-1600LG4077-Y21-G +
process16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways2 +
technologyCMOS +
thread count64 +
word size64 bit (8 octets, 16 nibbles) +