From WikiChip
Difference between revisions of "fujitsu/microarchitectures/post-k"
< fujitsu

(Architecture)
 
(One intermediate revision by the same user not shown)
Line 6: Line 6:
 
|manufacturer=TSMC
 
|manufacturer=TSMC
 
|introduction=2018
 
|introduction=2018
|cores=56
+
|cores=52
 
|type=Superscalar
 
|type=Superscalar
 
|type 2=Superpipeline
 
|type 2=Superpipeline
Line 21: Line 21:
  
 
== Architecture ==
 
== Architecture ==
Post-K is a custom-designed {{Arch|64}} [[ARM]] microprocessor.
+
Post-K is a custom-designed {{arch|64}} [[ARM]] microprocessor.
  
 
* ARMv8-A
 
* ARMv8-A
Line 27: Line 27:
 
*** Supports 512-bit vector operations
 
*** Supports 512-bit vector operations
 
* Many-core Architecture
 
* Many-core Architecture
** 56-cores/chip
+
** 52-cores/chip
 
*** 48 compute cores + assistant cores
 
*** 48 compute cores + assistant cores
 
* Memory
 
* Memory
 
** 3D stacked DRAM (HBM 3/4?)
 
** 3D stacked DRAM (HBM 3/4?)
 
*** Terabyte/s BW
 
*** Terabyte/s BW

Latest revision as of 10:45, 25 June 2018

Edit Values
Post-K µarch
General Info
Arch TypeCPU
DesignerFujitsu
ManufacturerTSMC
Introduction2018
Core Configs52
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAARMv8
ExtensionsSVE

Post-K is an ARM microarchitecture designed by Fujitsu for the Post-K


Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Architecture[edit]

Post-K is a custom-designed 64-bit ARM microprocessor.

  • ARMv8-A
    • SVE Extension
      • Supports 512-bit vector operations
  • Many-core Architecture
    • 52-cores/chip
      • 48 compute cores + assistant cores
  • Memory
    • 3D stacked DRAM (HBM 3/4?)
      • Terabyte/s BW