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Difference between revisions of "fujitsu/microarchitectures/post-k"
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{{fujitsu title|Post-K|arch}} | {{fujitsu title|Post-K|arch}} | ||
− | {{microarchitecture}} | + | {{microarchitecture |
+ | |atype=CPU | ||
+ | |name=Post-K | ||
+ | |designer=Fujitsu | ||
+ | |manufacturer=TSMC | ||
+ | |introduction=2018 | ||
+ | |cores=52 | ||
+ | |type=Superscalar | ||
+ | |type 2=Superpipeline | ||
+ | |oooe=Yes | ||
+ | |speculative=Yes | ||
+ | |renaming=Yes | ||
+ | |isa=ARMv8 | ||
+ | |extension=SVE | ||
+ | }} | ||
'''Post-K''' is an [[ARM]] microarchitecture designed by [[Fujitsu]] for the {{sc|Post-K|Post-K Supercomputer}} | '''Post-K''' is an [[ARM]] microarchitecture designed by [[Fujitsu]] for the {{sc|Post-K|Post-K Supercomputer}} | ||
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== Architecture == | == Architecture == | ||
− | Post-K is a custom-designed {{ | + | Post-K is a custom-designed {{arch|64}} [[ARM]] microprocessor. |
* ARMv8-A | * ARMv8-A | ||
Line 13: | Line 27: | ||
*** Supports 512-bit vector operations | *** Supports 512-bit vector operations | ||
* Many-core Architecture | * Many-core Architecture | ||
− | ** | + | ** 52-cores/chip |
*** 48 compute cores + assistant cores | *** 48 compute cores + assistant cores | ||
* Memory | * Memory | ||
** 3D stacked DRAM (HBM 3/4?) | ** 3D stacked DRAM (HBM 3/4?) | ||
*** Terabyte/s BW | *** Terabyte/s BW |
Latest revision as of 11:45, 25 June 2018
Edit Values | |
Post-K µarch | |
General Info | |
Arch Type | CPU |
Designer | Fujitsu |
Manufacturer | TSMC |
Introduction | 2018 |
Core Configs | 52 |
Pipeline | |
Type | Superscalar, Superpipeline |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | ARMv8 |
Extensions | SVE |
Post-K is an ARM microarchitecture designed by Fujitsu for the Post-K
Architecture[edit]
Post-K is a custom-designed 64-bit ARM microprocessor.
- ARMv8-A
- SVE Extension
- Supports 512-bit vector operations
- SVE Extension
- Many-core Architecture
- 52-cores/chip
- 48 compute cores + assistant cores
- 52-cores/chip
- Memory
- 3D stacked DRAM (HBM 3/4?)
- Terabyte/s BW
- 3D stacked DRAM (HBM 3/4?)
Facts about "Post-K - Microarchitectures - Fujitsu"
codename | Post-K + |
core count | 52 + |
designer | Fujitsu + |
first launched | 2018 + |
full page name | fujitsu/microarchitectures/post-k + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Post-K + |