Semiconductor & Computer Engineering
(→Overview) |
|||
| (4 intermediate revisions by 3 users not shown) | |||
| Line 1: | Line 1: | ||
{{cambricon title|MLU100}} | {{cambricon title|MLU100}} | ||
{{chip | {{chip | ||
| + | |chip type=neural processor | ||
|name=MLU100 | |name=MLU100 | ||
|image=cambricon mlu100 front.png | |image=cambricon mlu100 front.png | ||
| Line 20: | Line 21: | ||
== Overview == | == Overview == | ||
| − | In balanced mode which has a power envelope of 80 W, this processor has a theoretical peak performance of 128 trillion fixed-point (8-bit int) operations per second and 64 half-precision floating point (16-bit) TFLOPS. The efficiency of the chip slightly worsens at high-performance mode in favors of higher performances. In this mode the processor has a peak performance of 166.4 TOPS and 83.2 half-precision TFLOPS. | + | In balanced mode which has a power envelope of 80 W, this processor has a theoretical peak performance of 128 trillion fixed-point (8-bit int) operations per second and 64 half-precision floating point (16-bit) [[TFLOPS]]. The efficiency of the chip slightly worsens at high-performance mode in favors of higher performances. In this mode the processor has a peak performance of 166.4 TOPS and 83.2 half-precision TFLOPS. |
| + | |||
| + | <table class="wikitable"> | ||
| + | <tr><th> </th><th>Balanced Mode</th><th>High-Perf Mode</th></tr> | ||
| + | <tr><th>Frequency</th><td>1 GHz</td><td>1.3 GHz</td></tr> | ||
| + | <tr><th>8-bit Int</th><td>128 TOPS</td><td>166.4 TOPS</td></tr> | ||
| + | <tr><th>16-bit FP</th><td>64 TFLOPS</td><td>83.2 TFLOPS</td></tr> | ||
| + | </table> | ||
== Accelerator Card == | == Accelerator Card == | ||
Latest revision as of 10:06, 21 April 2019
| Edit Values | |
| MLU100 | |
 | |
| General Info | |
| Designer | Cambricon |
| Manufacturer | TSMC |
| Model Number | MLU100 |
| Market | Server |
| Introduction | November 7, 2017 (announced) May 3, 2018 (launched) |
| General Specs | |
| Family | MLU |
| Frequency | 1,000 MHZ, 1,300 MHz |
| Microarchitecture | |
| ISA | MLUv100 |
| Technology | CMOS |
| Electrical | |
| TDP | 80 W, 110 W |
MLU100 is a high-performance neural processor designed by Cambricon and introduced for the server market in mid-2018. The MLU100 is manufactured on TSMC's 16 nm process and operates at 1 GHz with a high-performance mode of 1.3 GHz.
Overview[edit]
In balanced mode which has a power envelope of 80 W, this processor has a theoretical peak performance of 128 trillion fixed-point (8-bit int) operations per second and 64 half-precision floating point (16-bit) TFLOPS. The efficiency of the chip slightly worsens at high-performance mode in favors of higher performances. In this mode the processor has a peak performance of 166.4 TOPS and 83.2 half-precision TFLOPS.
| Balanced Mode | High-Perf Mode | |
|---|---|---|
| Frequency | 1 GHz | 1.3 GHz |
| 8-bit Int | 128 TOPS | 166.4 TOPS |
| 16-bit FP | 64 TFLOPS | 83.2 TFLOPS |
Accelerator Card[edit]
Cambricon also sells the MLU100 in a PCIe accelerator card form factor. The x16 PCIe card comes in two versions with a 16 GiB and a 32 GiB of DDR4.
Memory controller[edit]
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
| base frequency | 1,300 MHz (1.3 GHz, 1,300,000 kHz) + |
| designer | Cambricon + |
| family | MLU + |
| first announced | November 7, 2017 + |
| first launched | May 3, 2018 + |
| full page name | cambricon/mlu/mlu100 + |
| has ecc memory support | true + |
| isa | MLUv100 + |
| ldate | May 3, 2018 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Server + |
| max memory bandwidth | 95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) + |
| max memory channels | 4 + |
| model number | MLU100 + |
| name | MLU100 + |
| supported memory type | DDR4-3200 + |
| tdp | 80 W (80,000 mW, 0.107 hp, 0.08 kW) + and 110 W (110,000 mW, 0.148 hp, 0.11 kW) + |
| technology | CMOS + |
