From WikiChip
Difference between revisions of "samsung/exynos/9810"
< samsung‎ | exynos

(→‎ISP =)
 
(25 intermediate revisions by 16 users not shown)
Line 11: Line 11:
 
|first launched=February 25, 2018
 
|first launched=February 25, 2018
 
|family=Exynos
 
|family=Exynos
−
|series=9000
+
|series=Exynos 9
−
|frequency=2,900 MHz
+
|frequency=2,704 MHz
−
|frequency 2=1,900 MHz
+
|frequency 2=1,794 MHz
−
|isa=ARMv8.3
+
|turbo frequency1=2,704 MHz
 +
|turbo frequency2=2,314 MHz
 +
|turbo frequency4=1,794 MHz
 +
|turbo frequency=2,704 MHz
 +
|max frequency=2,886 MHz
 +
|isa=ARMv8.2
 
|isa family=ARM
 
|isa family=ARM
−
|microarch=Mongoose 3
+
|isa 2=ARMv8.0
 +
|isa 2 family=ARM
 +
|microarch=Exynos M3
 
|microarch 2=Cortex-A55
 
|microarch 2=Cortex-A55
−
|core name=Mongoose 3
+
|core name=Meerkat
 
|core name 2=Cortex-A55
 
|core name 2=Cortex-A55
 
|process=10 nm
 
|process=10 nm
 
|technology=CMOS
 
|technology=CMOS
 +
|die area=118.94 mm²
 
|word size=64 bit
 
|word size=64 bit
 
|core count=8
 
|core count=8
 
|thread count=8
 
|thread count=8
 
|max cpus=1
 
|max cpus=1
 +
|predecessor=Exynos 8895
 +
|predecessor link=samsung/exynos/8895
 +
|successor=Exynos 9820
 +
|successor link=samsung/exynos/9820
 
}}
 
}}
−
'''Exynos 9810''' is a {{arch|64}} [[octa-core]] [[ARM]] performance microprocessor designed by [[Samsung]] and introduced in [[2018]] for their consumer electronics. The processor is fabricated on Samsung's [[10 nm process]] and features [[8 cores]] in a {{armh|DynamiQ}} configuration consisting of 4 {{samsung|Mongoose 3|l=arch}} cores operating at 2.9 GHz and 4 {{armh|Cortex-A55|l=arch}} cores operating at 1.9 GHz. The chip incorporates a {{armh|Mali G72|Mali-G72}} (MP18) GPU and a 1.2 Gbps [[LTE]] modem.
+
'''Exynos 9810''' is a {{arch|64}} [[octa-core]] [[ARM]] performance microprocessor designed by [[Samsung]] and introduced in [[2018]] for their consumer electronics. The processor is fabricated on Samsung's [[10 nm process]] and features [[8 cores]] in a configuration consisting of 4 {{samsung|Mongoose 3|l=arch}} [[big cores]] operating at 2.7 GHz (Up to 2.9 GHz) and 4 {{armh|Cortex-A55|l=arch}} [[little cores]] operating at 1.8 GHz (Up to 2 GHz). This chip supports up to 8 GiB of quad-channel 16-bit LPDDR4X-3588(MT/s) memory and incorporates a {{armh|Mali-G72}} MP18 GPU operating at 572 MHz. The 9810 incorporates an LTE modem supporting cat 18 download and cat 13 upload.
−
 
 
−
 
 
−
{{unknown features}}
 
  
  
Line 45: Line 54:
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l2 cache=2 MiB
 
|l2 cache=2 MiB
−
|l2 break=4x512 MiB
+
|l2 break=4x512 KiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l3 cache=4 MiB
 
|l3 cache=4 MiB
Line 68: Line 77:
 
== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=LPDDR4X-3600
+
|type=LPDDR4X-3588
 
|ecc=No
 
|ecc=No
−
|max mem=6 GiB
+
|max mem=8 GiB
 
|controllers=4
 
|controllers=4
−
|channels=4
+
|channels=2
−
|width=16 bit
+
|width=32 bit
−
|frequency=1800 MHz
+
|frequency=1794 MHz
−
|bandwidth schan=13.41 GiB/s
+
|bandwidth schan=13,36 GiB/s
−
|bandwidth dchan=26.82 GiB/s
+
|bandwidth dchan=26.72 GiB/s
 
}}
 
}}
  
Line 87: Line 96:
 
| max displays        = 2
 
| max displays        = 2
 
| max memory          =  
 
| max memory          =  
−
| frequency          = 600 MHz
+
| frequency          = 572 MHz
−
| max frequency      =  
+
| max frequency      = 598 MHz
  
 
| output crt          =  
 
| output crt          =  
Line 200: Line 209:
 
* [[used by::Samsung Galaxy S9]]
 
* [[used by::Samsung Galaxy S9]]
 
* [[used by::Samsung Galaxy S9+]]
 
* [[used by::Samsung Galaxy S9+]]
 +
* [[used by::Samsung Galaxy Note 9]]
 +
* [[used by::Samsung Galaxy Xcover FieldPro]]
 +
* [[used by::Samsung Galaxy Note 10 Lite]]
 +
* [[used by::Samsung Galaxy Tab Active3]]
  
−
{{expand list}}
+
{{expandlist}}

Latest revision as of 09:43, 7 March 2024

Edit Values
Exynos 9810
exynos 9810.png
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number9810
MarketMobile
IntroductionJanuary 3, 2018 (announced)
February 25, 2018 (launched)
General Specs
FamilyExynos
SeriesExynos 9
Frequency2,704 MHz, 1,794 MHz
Turbo Frequency2,704 MHz
Turbo Frequency2,704 MHz (1 core),
2,314 MHz (2 cores),
1,794 MHz (4 cores)
Microarchitecture
ISAARMv8.2 (ARM), ARMv8.0 (ARM)
MicroarchitectureExynos M3, Cortex-A55
Core NameMeerkat, Cortex-A55
Process10 nm
TechnologyCMOS
Die118.94 mm²
Word Size64 bit
Cores8
Threads8
Multiprocessing
Max SMP1-Way (Uniprocessor)
Succession

Exynos 9810 is a 64-bit octa-core ARM performance microprocessor designed by Samsung and introduced in 2018 for their consumer electronics. The processor is fabricated on Samsung's 10 nm process and features 8 cores in a configuration consisting of 4 Mongoose 3 big cores operating at 2.7 GHz (Up to 2.9 GHz) and 4 Cortex-A55 little cores operating at 1.8 GHz (Up to 2 GHz). This chip supports up to 8 GiB of quad-channel 16-bit LPDDR4X-3588(MT/s) memory and incorporates a Mali-G72 MP18 GPU operating at 572 MHz. The 9810 incorporates an LTE modem supporting cat 18 download and cat 13 upload.


Cache[edit]

Main articles: Mongoose 3 § Cache and Cortex-A55 § Cache

For the Mongoose 3 core cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$256 KiB
262,144 B
0.25 MiB
4x64 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  4x512 KiB16-way set associative 
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  1x4 MiB  

For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB2-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associative 
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3588
Supports ECCNo
Max Mem8 GiB
Frequency1794 MHz
Controllers4
Channels2
Width32 bit
Bandwidth
Single 13,36 GiB/s
Double 26.72 GiB/s

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G72
DesignerARM Holdings
Execution Units18Max Displays2
Frequency572 MHz
0.572 GHz
572,000 KHz
Burst Frequency598 MHz
0.598 GHz
598,000 KHz
OutputDSI
Standards
DirectX12
OpenCL2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0


Codec Encode Decode
HEVC (H.265) ✔ ✔
MPEG-4 AVC (H.264) ✔ ✔
VP9 ✔ ✔

All at 4K UHD 120fps.

Wireless[edit]

Antu network-wireless-connected-100.svgWireless Communications
Cellular
4G
LTE Advanced
UE Cat DL18 (1200 Mbps)
UE Cat UL13 (200 Mbps)

ISP[edit]

  • 24MP Rear
  • 24MP Front
  • 16MP+16MP Dual

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension

Utilizing devices[edit]

  • Samsung Galaxy S9
  • Samsung Galaxy S9+
  • Samsung Galaxy Note 9
  • Samsung Galaxy Xcover FieldPro
  • Samsung Galaxy Note 10 Lite
  • Samsung Galaxy Tab Active3

Template:expandlist

Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/9810&oldid=102366"
Facts about "Exynos 9810 - Samsung"
RDF feed
base frequency2,900 MHz (2.9 GHz, 2,900,000 kHz) + and 1,900 MHz (1.9 GHz, 1,900,000 kHz) +
core count8 +
core nameMongoose 3 + and Cortex-A55 +
designerSamsung + and ARM Holdings +
familyExynos +
first announcedJanuary 3, 2018 +
first launchedFebruary 25, 2018 +
full page namesamsung/exynos/9810 +
has 4g supporttrue +
has ecc memory supportfalse +
has lte advanced supporttrue +
instance ofmicroprocessor +
integrated gpuMali-G72 +
integrated gpu base frequency600 MHz (0.6 GHz, 600,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units18 +
isaARMv8.3 +
isa familyARM +
l1$ size384 KiB (393,216 B, 0.375 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative + and 4-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative + and 2-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateFebruary 25, 2018 +
main imageFile:exynos 9810.png +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max memory channels4 +
microarchitectureMongoose 3 + and Cortex-A55 +
model number9810 +
nameExynos 9810 +
process10 nm (0.01 μm, 1.0e-5 mm) +
series9000 +
smp max ways1 +
supported memory typeLPDDR4X-3600 +
technologyCMOS +
thread count8 +
used bySamsung Galaxy S9 + and Samsung Galaxy S9+ +
user equipment category downlink18 +
user equipment category uplink13 +
word size64 bit (8 octets, 16 nibbles) +