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Difference between revisions of "movidius/myriad/ma1110"
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{{movidius title|Myriad 1 MA1110}} | {{movidius title|Myriad 1 MA1110}} | ||
{{chip | {{chip | ||
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|name=Myriad 1 MA1110 | |name=Myriad 1 MA1110 | ||
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|technology=TSMC | |technology=TSMC | ||
|word size=32 bit | |word size=32 bit | ||
| − | |core count= | + | |core count=9 |
| − | |thread count=1 | + | |thread count=9 |
| + | |v core=1.2 V | ||
| + | |v io=2.5 V | ||
}} | }} | ||
'''Myriad 1 MA1110''' was a vision processing [[accelerator]] designed by [[Movidius]] and introduced in [[2009]]. | '''Myriad 1 MA1110''' was a vision processing [[accelerator]] designed by [[Movidius]] and introduced in [[2009]]. | ||
| + | |||
| + | == Overview == | ||
| + | The MA1110 is a vision [[accelerator]] designed to work alongside a main host processors, typically in a mobile or embedded device. The MA1110 consists of a single [[SPARC]] {{sparc|V8}} [[LEON3]] core which is used for management and control and eight {{movidius|SHAVE v2.0|l=arch}} core which are the workhorse of this chip. Each core has 128 KiB of cache. The eight SHAVE cores together are capable of 20GFLOPS of processing power at just a few 100s milliwatt of power. | ||
| + | |||
| + | [[File:movidius ma1000 silicon platform.png|600px]] | ||
| + | |||
| + | == Extensions == | ||
| + | * Host Memory Bus (master and slave): 8-bit / 16-bit / 32-bit | ||
| + | * Video Output Formats: | ||
| + | ** 8-24 bit RGB, CPU (Intel/Motorola), BT656 ... | ||
| + | ** 24bpp, 16M colors, resolutions up to 2048x2048 | ||
| + | ** Video support for 4 layers of video and graphics | ||
| + | * External TV Support | ||
| + | ** Video Output to External HDMI Driver Chip | ||
| + | * Multiple I2S (Master/Slave) stereo audio channels | ||
| + | ** Independent sampling frequencies | ||
| + | * Standard interfaces | ||
| + | ** I2C, UART, SDIO, SPI | ||
| + | * Configurable bidirectional GPIO lanes | ||
Latest revision as of 14:36, 11 March 2018
| Edit Values | |
| Myriad 1 MA1110 | |
| General Info | |
| Designer | Movidius |
| Manufacturer | TSMC |
| Model Number | MA1110 |
| Market | Embedded, Mobile |
| Introduction | January 15, 2009 (announced) June, 2009 (launched) |
| General Specs | |
| Family | Myriad |
| Series | 1 |
| Frequency | 180 MHz |
| Microarchitecture | |
| ISA | SPARC V8 (SPARC), SHAVE (SHAVE) |
| Microarchitecture | LEON3, SHAVE v2.0 |
| Process | 65 nm |
| Technology | TSMC |
| Word Size | 32 bit |
| Cores | 9 |
| Threads | 9 |
| Electrical | |
| Vcore | 1.2 V |
| VI/O | 2.5 V |
Myriad 1 MA1110 was a vision processing accelerator designed by Movidius and introduced in 2009.
Overview[edit]
The MA1110 is a vision accelerator designed to work alongside a main host processors, typically in a mobile or embedded device. The MA1110 consists of a single SPARC V8 LEON3 core which is used for management and control and eight SHAVE v2.0 core which are the workhorse of this chip. Each core has 128 KiB of cache. The eight SHAVE cores together are capable of 20GFLOPS of processing power at just a few 100s milliwatt of power.
Extensions[edit]
- Host Memory Bus (master and slave): 8-bit / 16-bit / 32-bit
- Video Output Formats:
- 8-24 bit RGB, CPU (Intel/Motorola), BT656 ...
- 24bpp, 16M colors, resolutions up to 2048x2048
- Video support for 4 layers of video and graphics
- External TV Support
- Video Output to External HDMI Driver Chip
- Multiple I2S (Master/Slave) stereo audio channels
- Independent sampling frequencies
- Standard interfaces
- I2C, UART, SDIO, SPI
- Configurable bidirectional GPIO lanes
Facts about "Myriad 1 MA1110 - Intel Movidius"
| full page name | movidius/myriad/ma1110 + |
| instance of | microprocessor + |
| ldate | 1900 + |