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Difference between revisions of "amd/epyc embedded/3401"
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|family=EPYC Embedded
 
|family=EPYC Embedded
 
|series=3000
 
|series=3000
 +
|locked=Yes
 
|frequency=1,850 MHz
 
|frequency=1,850 MHz
 
|turbo frequency1=3,000 MHz
 
|turbo frequency1=3,000 MHz
 +
|turbo frequency16=2,250 MHz
 
|clock multiplier=18.5
 
|clock multiplier=18.5
 
|isa=x86-64
 
|isa=x86-64
Line 19: Line 21:
 
|microarch=Zen
 
|microarch=Zen
 
|core name=Snowy Owl
 
|core name=Snowy Owl
 +
|core family=23
 +
|core model=1
 +
|core stepping=B2
 +
|cpuid=0x00800F12
 
|process=14 nm
 
|process=14 nm
 
|transistors=9,600,000,000
 
|transistors=9,600,000,000
Line 33: Line 39:
 
|tjunc min=0 °C
 
|tjunc min=0 °C
 
|tjunc max=105 °C
 
|tjunc max=105 °C
−
|package module 1={{packages/amd/package sp4}}
+
|package name 1=amd,sp4
 
}}
 
}}
−
'''EPYC Embedded 3401''' is a {{arch|64}} [[hexadeca-core]] [[x86]] embedded microprocessor introduced by [[AMD]] in early [[2018]] for dense servers and edge devices. Fabricated on a [[14 nm process]] based on the {{amd|Zen|Zen microarchitecture|l=arch}}, this chip operates at 1.85 GHz with a TDP of 85 W and a {{amd|precision boost|turbo frequency}} of up to 3 GHz. The 3401 supports up to 1 TiB of quad-channel DDR4-2666 ECC memory.
+
'''EPYC Embedded 3401''' is a {{arch|64}} [[16-core]] [[x86]] embedded microprocessor introduced by [[AMD]] in early [[2018]] for dense servers and edge devices. This [[multi-chip package|multi-chip processor]] has CPU cores based on the {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[GlobalFoundries]] [[14 nm#GlobalFoundries|14&nbsp;nm]] process. It operates at 1.85 GHz with a {{abbr|TDP}} of 85 W and a {{amd|precision boost|turbo frequency}} of up to 3.0 GHz. The 3401 supports up to 1 TiB of quad-channel DDR4-2666 memory.
−
 
 
−
 
 
−
{{unknown features}}
 
  
 +
This model was apparently canceled.
  
 
== Cache ==
 
== Cache ==
 
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
 
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
 
{{cache size
 
{{cache size
−
|l1 cache=1.5 MiB
+
|l1 cache=1536 KiB
 
|l1i cache=1 MiB
 
|l1i cache=1 MiB
−
|l1i break=16x64 KiB
+
|l1i break=16 × 64 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
 
|l1d cache=512 KiB
 
|l1d cache=512 KiB
−
|l1d break=16x32 KiB
+
|l1d break=16 × 32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d policy=write-back
 
|l1d policy=write-back
 
|l2 cache=8 MiB
 
|l2 cache=8 MiB
−
|l2 break=16x512 KiB
+
|l2 break=16 × 512 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back
 
|l3 cache=32 MiB
 
|l3 cache=32 MiB
−
|l3 break=4x8 MiB
+
|l3 break=4 × 8 MiB
 
|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
Line 69: Line 73:
 
|controllers=4
 
|controllers=4
 
|channels=4
 
|channels=4
−
|max bandwidth=79.47 GiB/s
+
|max bandwidth=85.33 GB/s
−
|bandwidth schan=19.87 GiB/s
+
|bandwidth schan=21.33 GB/s
−
|bandwidth dchan=39.74 GiB/s
+
|bandwidth dchan=42.67 GB/s
−
|bandwidth qchan=79.47 GiB/s
+
|bandwidth qchan=85.33 GB/s
 
}}
 
}}
  
−
{{amd ryzen threadripper memory configs}}
 
 
== Expansions ==
 
== Expansions ==
−
The EPYC Embedded 3401 has 64 PCIe lanes that are MUX'ed with a number of other ports and can be reconfigured as either SATA ports (up to 16 such ports), or as GbE ports (up to 10 such ports), or any mixed configuration of those options.
+
The EPYC Embedded 3401 integrates four 8-port, 16-lane PCIe Gen 1/2/3 (8 GT/s) controllers. All lanes are configurable as x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) PCIe links, some lanes alternatively as SATA Gen 1/2/3 (6 Gb/s) or 10 Gbit/s Ethernet ports. Up to sixteen SATA ports and eight GbE ports are available on this model, as well as four USB 3.1 Gen 1 (5 Gb/s) ports, and the following low speed interfaces: {{abbr|eMMC}}, {{abbr|UART}}, {{abbr|LPC}}, {{abbr|SPI/eSPI}}, {{abbr|I<sup>2</sup>C}}, {{abbr|SMBus}}, {{abbr|GPIO}}.
 +
 
 
{{expansions main
 
{{expansions main
 
|
 
|
Line 88: Line 92:
 
|pcie config 3=x4
 
|pcie config 3=x4
 
|pcie config 4=x2
 
|pcie config 4=x2
 +
|pcie config 5=x1
 +
}}
 +
{{expansions entry
 +
|type=USB
 +
|usb revision=3.1
 +
|usb ports=4
 
}}
 
}}
 
{{expansions entry
 
{{expansions entry
Line 98: Line 108:
 
|eth opts=Yes
 
|eth opts=Yes
 
|10ge=Yes
 
|10ge=Yes
−
|10ge ports=4
+
|10ge ports=8
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=Yes
 +
|sse_gfni=No
 +
|avx=Yes
 +
|avx_gfni=No
 +
|avx2=Yes
 +
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512gfni=No
 +
|avx512vaes=No
 +
|avx512vbmi2=No
 +
|avx512bitalg=No
 +
|avx512vpclmulqdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=Yes
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|tvb=No
 +
|bpt=No
 +
|eist=No
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=Yes
 +
|amdv=Yes
 +
|amdsme=Yes
 +
|amdtsme=Yes
 +
|amdsev=Yes
 +
|rvi=No
 +
|smt=No
 +
|sensemi=Yes
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 
}}
 
}}
 +
 +
== Bibliography ==
 +
* {{cite techdoc|title=Product Brief: AMD EPYC™ Embedded 3000 Family|file=3000-Family-Product-Brief.pdf|publ=AMD|pid=1887102|date=2018}}
 +
* {{cite techdoc|title=Product Brief: AMD EPYC™ Embedded 3000 Family|url=https://www.amd.com/system/files/documents/updated-3000-family-product-brief.pdf|publ=AMD|pid=1887102|rev=E|date=2019}}
 +
* [https://www.amd.com/en/products/specifications/embedded "Embedded Processor Specifications"]. AMD.com. Retrieved October 2020.

Latest revision as of 04:20, 24 March 2023

Edit Values
EPYC Embedded 3401
General Info
DesignerAMD
ManufacturerGlobalFoundries
Model Number3401
MarketServer, Embedded
IntroductionFebruary 21, 2018 (announced)
February 21, 2018 (launched)
ShopAmazon
General Specs
FamilyEPYC Embedded
Series3000
LockedYes
Frequency1,850 MHz
Turbo Frequency3,000 MHz (1 core),
2,250 MHz (16 cores)
Clock multiplier18.5
CPUID0x00800F12
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen
Core NameSnowy Owl
Core Family23
Core Model1
Core SteppingB2
Process14 nm
Transistors9,600,000,000
TechnologyCMOS
Die213 mm²
MCPYes (2 dies)
Word Size64 bit
Cores16
Threads16
Max Memory1 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP85 W
Tjunction0 °C – 105 °C
Packaging
PackageSP4 (FC-OBGA)
Dimension45 mm × 45 mm
Pitch0.8 mm

EPYC Embedded 3401 is a 64-bit 16-core x86 embedded microprocessor introduced by AMD in early 2018 for dense servers and edge devices. This multi-chip processor has CPU cores based on the Zen microarchitecture and is fabricated on a GlobalFoundries 14 nm process. It operates at 1.85 GHz with a TDP of 85 W and a turbo frequency of up to 3.0 GHz. The 3401 supports up to 1 TiB of quad-channel DDR4-2666 memory.

This model was apparently canceled.

Cache[edit]

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1536 KiB
1,572,864 B
1.5 MiB
L1I$1 MiB
1,024 KiB
1,048,576 B
16 × 64 KiB4-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16 × 32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  16 × 512 KiB8-way set associativewrite-back
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  4 × 8 MiB16-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem1 TiB
Controllers4
Channels4
Max Bandwidth85.33 GB/s
79.47 GiB/s
81,377.029 MiB/s
85,330 MB/s
0.0776 TiB/s
0.0853 TB/s
Bandwidth
Single 21.33 GB/s
Double 42.67 GB/s
Quad 85.33 GB/s

Expansions[edit]

The EPYC Embedded 3401 integrates four 8-port, 16-lane PCIe Gen 1/2/3 (8 GT/s) controllers. All lanes are configurable as x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) PCIe links, some lanes alternatively as SATA Gen 1/2/3 (6 Gb/s) or 10 Gbit/s Ethernet ports. Up to sixteen SATA ports and eight GbE ports are available on this model, as well as four USB 3.1 Gen 1 (5 Gb/s) ports, and the following low speed interfaces: eMMC, UART, LPC, SPI/eSPI, I2C, SMBus, GPIO.

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 64
Configuration: x16, x8, x4, x2, x1
USBRevision: 3.1
Max Ports: 4
SATARevision: 3.0
Max Ports: 16

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
Ethernet
10GbEYes (Ports: 8)

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SMESecure Memory Encryption
TSMETransparent SME
SEVSecure Encrypted Virtualization
SenseMISenseMI Technology

Bibliography[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc_embedded/3401&oldid=101386"
Facts about "EPYC Embedded 3401 - AMD"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC Embedded 3401 - AMD#pcie +
base frequency1,850 MHz (1.85 GHz, 1,850,000 kHz) +
clock multiplier18.5 +
core count16 +
core family23 +
core model1 +
core nameSnowy Owl +
core steppingB2 +
cpuid0x00800F12 +
designerAMD +
die area213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count2 +
familyEPYC Embedded +
first announcedFebruary 21, 2018 +
first launchedFebruary 21, 2018 +
full page nameamd/epyc embedded/3401 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has locked clock multipliertrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description4-way set associative +
l1i$ size1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateFebruary 21, 2018 +
manufacturerGlobalFoundries +
market segmentServer + and Embedded +
max cpu count1 +
max junction temperature378.15 K (105 °C, 221 °F, 680.67 °R) +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth79.47 GiB/s (81,377.029 MiB/s, 85.33 GB/s, 85,330 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels4 +
max sata ports16 +
max usb ports4 +
microarchitectureZen +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number3401 +
nameEPYC Embedded 3401 +
packageSP4 +
process14 nm (0.014 μm, 1.4e-5 mm) +
series3000 +
smp max ways1 +
supported memory typeDDR4-2666 +
tdp85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technologyCMOS +
thread count16 +
transistor count9,600,000,000 +
turbo frequency (16 cores)2,250 MHz (2.25 GHz, 2,250,000 kHz) +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +