From WikiChip
Difference between revisions of "intel/xeon d/d-2166nt"
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|isa family=x86 | |isa family=x86 | ||
|microarch=Skylake (server) | |microarch=Skylake (server) | ||
− | |core name=Skylake | + | |core name=Skylake DE |
|core stepping=M1 | |core stepping=M1 | ||
|process=14 nm | |process=14 nm | ||
Line 37: | Line 37: | ||
|max memory=512 GiB | |max memory=512 GiB | ||
|tdp=85 W | |tdp=85 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=90 °C | ||
|package module 1={{packages/intel/fcbga-2518}} | |package module 1={{packages/intel/fcbga-2518}} | ||
}} | }} | ||
− | '''Xeon D-2166NT''' is a {{arch|64}} [[12-core]] high-performance [[x86]] server microprocessor introduced by [[Intel]] in early 2018 for the dense server and [[edge computing]] market segment. Fabricated on Intel's [[14 nm process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture, this model operates at 2.0 GHz with a {{intel|Turbo Boost}} of up to 3.0 GHz and a [[TDP]] of 85 W. The D-2166NT supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory. | + | '''Xeon D-2166NT''' is a {{arch|64}} [[12-core]] high-performance [[x86]] server microprocessor introduced by [[Intel]] in early 2018 for the dense server and [[edge computing]] market segment. Fabricated on Intel's [[14 nm process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture, this model operates at 2.0 GHz with a {{intel|Turbo Boost}} of up to 3.0 GHz and a [[TDP]] of 85 W. The D-2166NT supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory. This model is part of {{intel|Skylake DE|l=core}}'s [[part of::Integrated QuickAssist Technology SKUs]]. |
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|l3 desc=11-way set associative | |l3 desc=11-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2133 | ||
+ | |ecc=Yes | ||
+ | |max mem=512 GiB | ||
+ | |controllers=2 | ||
+ | |channels=4 | ||
+ | |max bandwidth=79.47 GiB/s | ||
+ | |bandwidth schan=15.89 GiB/s | ||
+ | |bandwidth dchan=31.78 GiB/s | ||
+ | |bandwidth qchan=63.57 GiB/s | ||
+ | |pae=46 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 [[PCIe]] lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports. | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=32 | ||
+ | |pcie config=x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
+ | {{expansions entry | ||
+ | |type=HSIO | ||
+ | |hsio lanes=20 | ||
+ | }} | ||
+ | }} | ||
+ | == Networking == | ||
+ | {{network | ||
+ | |eth opts=Yes | ||
+ | |10ge=Yes | ||
+ | |10ge ports=4 | ||
+ | }} | ||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |avx512units=1 | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=Yes | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=Yes | ||
+ | |sgx=No | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |intqat=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,000 MHz | ||
+ | |freq_1=3,000 MHz | ||
+ | |freq_2=3,000 MHz | ||
+ | |freq_3=2,800 MHz | ||
+ | |freq_4=2,800 MHz | ||
+ | |freq_5=2,600 MHz | ||
+ | |freq_6=2,600 MHz | ||
+ | |freq_7=2,600 MHz | ||
+ | |freq_8=2,600 MHz | ||
+ | |freq_9=2,300 MHz | ||
+ | |freq_10=2,300 MHz | ||
+ | |freq_11=2,300 MHz | ||
+ | |freq_12=2,300 MHz | ||
+ | |freq_avx2_1=2,900 MHz | ||
+ | |freq_avx2_2=2,900 MHz | ||
+ | |freq_avx2_3=2,700 MHz | ||
+ | |freq_avx2_4=2,700 MHz | ||
+ | |freq_avx2_5=2,400 MHz | ||
+ | |freq_avx2_6=2,400 MHz | ||
+ | |freq_avx2_7=2,400 MHz | ||
+ | |freq_avx2_8=2,400 MHz | ||
+ | |freq_avx2_9=2,100 MHz | ||
+ | |freq_avx2_10=2,100 MHz | ||
+ | |freq_avx2_11=2,100 MHz | ||
+ | |freq_avx2_12=2,100 MHz | ||
+ | |freq_avx512_1=2,800 MHz | ||
+ | |freq_avx512_2=2,800 MHz | ||
+ | |freq_avx512_3=2,600 MHz | ||
+ | |freq_avx512_4=2,600 MHz | ||
+ | |freq_avx512_5=2,200 MHz | ||
+ | |freq_avx512_6=2,200 MHz | ||
+ | |freq_avx512_7=2,200 MHz | ||
+ | |freq_avx512_8=2,200 MHz | ||
+ | |freq_avx512_9=1,900 MHz | ||
+ | |freq_avx512_10=1,900 MHz | ||
+ | |freq_avx512_11=1,900 MHz | ||
+ | |freq_avx512_12=1,900 MHz | ||
}} | }} |
Latest revision as of 00:08, 8 February 2018
Edit Values | |||||||
Xeon D-2166NT | |||||||
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General Info | |||||||
Designer | Intel | ||||||
Manufacturer | Intel | ||||||
Model Number | D-2166NT | ||||||
Part Number | FH8067303784301 | ||||||
S-Spec | SR3ZX | ||||||
Market | Server, Embedded | ||||||
Introduction | February 7, 2018 (announced) February 7, 2018 (launched) | ||||||
Release Price | $1,005.00 | ||||||
Shop | Amazon | ||||||
General Specs | |||||||
Family | Xeon D | ||||||
Series | D-2000 | ||||||
Locked | Yes | ||||||
Frequency | 2,000 MHz | ||||||
Turbo Frequency | 3,000 MHz (1 core) | ||||||
Bus type | DMI 3.0 | ||||||
Bus rate | 4 × 8 GT/s | ||||||
Clock multiplier | 20 | ||||||
Microarchitecture | |||||||
ISA | x86-64 (x86) | ||||||
Microarchitecture | Skylake (server) | ||||||
Core Name | Skylake DE | ||||||
Core Stepping | M1 | ||||||
Process | 14 nm | ||||||
Technology | CMOS | ||||||
MCP | Yes (2 dies) | ||||||
Word Size | 64 bit | ||||||
Cores | 12 | ||||||
Threads | 24 | ||||||
Max Memory | 512 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Electrical | |||||||
TDP | 85 W | ||||||
Tcase | 0 °C – 90 °C | ||||||
Packaging | |||||||
|
Xeon D-2166NT is a 64-bit 12-core high-performance x86 server microprocessor introduced by Intel in early 2018 for the dense server and edge computing market segment. Fabricated on Intel's 14 nm process based on the Skylake microarchitecture, this model operates at 2.0 GHz with a Turbo Boost of up to 3.0 GHz and a TDP of 85 W. The D-2166NT supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory. This model is part of Skylake DE's Integrated QuickAssist Technology SKUs.
Cache[edit]
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 PCIe lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.
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Expansion Options |
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Networking[edit]
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Networking
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 2,000 MHz | 3,000 MHz | 3,000 MHz | 2,800 MHz | 2,800 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,300 MHz | 2,300 MHz | 2,300 MHz | 2,300 MHz |
AVX2 | 2,900 MHz | 2,900 MHz | 2,700 MHz | 2,700 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,400 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz | |
AVX512 | 2,800 MHz | 2,800 MHz | 2,600 MHz | 2,600 MHz | 2,200 MHz | 2,200 MHz | 2,200 MHz | 2,200 MHz | 1,900 MHz | 1,900 MHz | 1,900 MHz | 1,900 MHz |
Facts about "Xeon D-2166NT - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon D-2166NT - Intel#package + |
base frequency | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 20 + |
core count | 12 + |
core name | Skylake-DE + |
core stepping | M1 + |
designer | Intel + |
die count | 2 + |
family | Xeon D + |
first announced | February 7, 2018 + |
first launched | February 7, 2018 + |
full page name | intel/xeon d/d-2166nt + |
has ecc memory support | true + |
has locked clock multiplier | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) + |
ldate | February 7, 2018 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + and Embedded + |
max cpu count | 1 + |
max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
max memory channels | 4 + |
microarchitecture | Skylake (server) + |
model number | D-2166NT + |
name | Xeon D-2166NT + |
package | FCBGA-2518 + |
part number | FH8067303784301 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,005.00 (€ 904.50, £ 814.05, ¥ 103,846.65) + |
s-spec | SR3ZX + |
series | D-2000 + |
smp max ways | 1 + |
supported memory type | DDR4-2133 + |
tdp | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
technology | CMOS + |
thread count | 24 + |
turbo frequency (1 core) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |