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Difference between revisions of "ampere computing/emag/8180"
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a1{{ampere title|A1}}
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{{ampere title|eMAG 8180}}
 
{{chip
 
{{chip
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|future=Yes
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|name=eMAG 8180
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|name=A1
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|image=emag (front).jpg
−
|image=ampere a1.png
 
 
|designer=Ampere Computing
 
|designer=Ampere Computing
 
|manufacturer=TSMC
 
|manufacturer=TSMC
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|model number=A1
+
|model number=8180
 
|market=Server
 
|market=Server
 
|first announced=February 5, 2018
 
|first announced=February 5, 2018
−
|release price=$950
+
|first launched=September 8, 2018
 +
|release price=$850
 +
|family=eMAG
 +
|series=eMAG 1
 +
|frequency=3,000 MHz
 
|turbo frequency=3,300 MHz
 
|turbo frequency=3,300 MHz
 
|isa=ARMv8
 
|isa=ARMv8
 
|isa family=ARM
 
|isa family=ARM
 +
|microarch=Skylark
 
|process=16 nm
 
|process=16 nm
 
|technology=CMOS
 
|technology=CMOS
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|package module 1={{packages/ampere_computing/fcbga-3211}}
 
|package module 1={{packages/ampere_computing/fcbga-3211}}
 
}}
 
}}
−
'''A1''' is a {{arch|64}} [[32-core]] [[ARM]] server microprocessor introduced by [[ampere computing|Ampere]] in [[2018]]. Fabricated on [[TSMC]]'s [[16 nm process|16FF+]], this processor operates at ? with a turbo frequency of up to 3.3 GHz and 125 W TDP. This processor supports up to 8 channels of DDR4-2666 ECC memory.
+
'''eMAG 8180''' is a {{arch|64}} [[dotriaconta-core]] [[ARM]] server microprocessor introduced by [[ampere computing|Ampere]] in [[2018]]. Fabricated on [[TSMC]]'s [[16 nm process|16FF+]] based on the {{apm|Skylark|l=arch}} microarchitecture, this processor operates at 3 GHz with a TDP of 125 W and a turbo of up to 3.3 GHz. This processor supports up to 8 channels of DDR4-2666 memory.
 +
 
 +
== Cache ==
 +
{{main|apm/microarchitectures/skylark#Memory_Hierarchy|l1=Skylark § Cache}}
 +
{{cache size
 +
|l1 cache=2 MiB
 +
|l1i cache=1 MiB
 +
|l1i break=32x32 KiB
 +
|l1d cache=1 MiB
 +
|l1d break=32x32 KiB
 +
|l1d policy=write-through
 +
|l2 cache=4 MiB
 +
|l2 break=16x256 KiB
 +
|l3 cache=32 MiB
 +
|l3 break=1x32 MiB
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|type 2=DDR4-2400
 +
|ecc=Yes
 +
|max mem=1 TiB
 +
|controllers=8
 +
|channels=8
 +
|max bandwidth=158.95 GiB/s
 +
|bandwidth schan=19.89 GiB/s
 +
|bandwidth dchan=39.72 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
|bandwidth ochan=158.95 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
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|type=PCIe
 +
|pcie revision=3.0
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|pcie lanes=42
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|pcie config=x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
{{expansions entry
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|type=USB
 +
|usb revision=2.0
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|usb ports=2
 +
}}
 +
{{expansions entry
 +
|type=SATA
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|sata revision=3
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|sata ports=4
 +
}}
 +
}}
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 +
== Features ==
 +
{{arm features
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|thumb=No
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|thumb2=No
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|thumbee=No
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|vfpv1=No
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|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=No
 +
|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
 +
|trustzone=Yes
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|jazelle=No
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|wmmx=No
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|wmmx2=No
 +
|pmuv3=No
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|crc32=No
 +
|crypto=Yes
 +
|fp=Yes
 +
|fp16=No
 +
|profile=No
 +
|ras=No
 +
|simd=No
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|rdm=No
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}}
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 +
== Block Diagram ==
 +
[[File:ampere a1 block diagram.png|750px]]
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 +
== Documents ==
 +
* [[:File:eMAG8180 PB.pdf|Product Brief]]

Latest revision as of 02:00, 26 September 2018

Edit Values
eMAG 8180
emag (front).jpg
General Info
DesignerAmpere Computing
ManufacturerTSMC
Model Number8180
MarketServer
IntroductionFebruary 5, 2018 (announced)
September 8, 2018 (launched)
Release Price$850
General Specs
FamilyeMAG
SerieseMAG 1
Frequency3,000 MHz
Turbo Frequency3,300 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureSkylark
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores32
Threads32
Max Memory1 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.85 V
VI/O1.8, 3.3
TDP125 W
Tjunction0 °C – 90 °C
Packaging
PackageFCBGA-3211 (BGA)
Dimension50 mm x 50 mm
Contacts3,211

eMAG 8180 is a 64-bit dotriaconta-core ARM server microprocessor introduced by Ampere in 2018. Fabricated on TSMC's 16FF+ based on the Skylark microarchitecture, this processor operates at 3 GHz with a TDP of 125 W and a turbo of up to 3.3 GHz. This processor supports up to 8 channels of DDR4-2666 memory.

Cache[edit]

Main article: Skylark § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2 MiB
2,048 KiB
2,097,152 B
L1I$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB  
L1D$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB write-through
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  16x256 KiB  
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  1x32 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666, DDR4-2400
Supports ECCYes
Max Mem1 TiB
Controllers8
Channels8
Max Bandwidth158.95 GiB/s
162,764.8 MiB/s
170.671 GB/s
170,671.263 MB/s
0.155 TiB/s
0.171 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Octa 158.95 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 42
Configuration: x16, x8, x4
USBRevision: 2.0
Max Ports: 2
SATARevision: 3
Max Ports: 4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions
CryptoCryptographic Extension
FPFloating-point Extension

Block Diagram[edit]

ampere a1 block diagram.png

Documents[edit]

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