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{{nervana title|Lake Crest|arch}}
 
{{nervana title|Lake Crest|arch}}
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{{microarchitecture}}
+
{{microarchitecture
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|atype=NPU
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|name=Lake Crest
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|designer=Nervana
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|manufacturer=TSMC
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|introduction=November 17, 2016
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|process=28 nm
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|successor=Spring Crest
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|successor link=nervana/microarchitectures/spring crest
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}}
 
'''Lake Crest''' is a [[neural processor]] microarchitecture designed by [[Nervana]].
 
'''Lake Crest''' is a [[neural processor]] microarchitecture designed by [[Nervana]].
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== Process Technology ==
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Lake Crest is fabricated on [[TSMC]]'s [[28 nm process]].
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== Architecture ==
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Lake Crest was designed from the ground up for [[deep learning]]. The architecture itself is a tensor-based architecture, meaning it's optimized for blocks of compute instead of operating on scalars (as would a traditional Intel CPU would).
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* Tensor-based architecture
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** Nervana Engine
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* [[Flexpoint]] number format
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* No caches
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** Software explicitly manages all on-chip memory
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* HBM2 memory
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** 32 GiB of in-package memory
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** 8 Tbit/s bandwidth
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* 12 x Inter-Chip Links (ICL)
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** bi-directional high-bandwidth direct chip-to-chip interconnect
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** 100 GB/s (1,200 GB/s aggregate)
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{{expand list}}
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=== Block Diagram ===
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==== Chip ====
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:[[File:knights crest chip block diagram.svg|700px]]
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==== Processing Cluster ====
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{{empty section}}
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=== Memory Hierarchy ===
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* 32 GiB on-package [[HBM2]]
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** 1 TiB/s
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== Die ==
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Nervana stated that Lake Crest is "near-reticle size" implying the die size is likely around the 650-750 mm².
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* TSMC [[28 nm process]]
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* 650-750 mm² die size
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== Additional Shots ==
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<gallery mode=slideshow>
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File:lake crest pcie card internal.png|Lake Crest Accelerator PCIe card (internal view)
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</gallery>
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== Bibliography ==
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* Rao, N. (2016, November). ''Pathfinding and Hardware Deep Dive''. 2016 AI Day, San Francisco.
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* Rao, N. (2018, May). ''Keynote presentation''. 2018 AI DevCon, San Francisco.

Latest revision as of 15:51, 6 August 2020

Edit Values
Lake Crest µarch
General Info
Arch TypeNPU
DesignerNervana
ManufacturerTSMC
IntroductionNovember 17, 2016
Process28 nm
Succession

Lake Crest is a neural processor microarchitecture designed by Nervana.

Process Technology[edit]

Lake Crest is fabricated on TSMC's 28 nm process.

Architecture[edit]

Lake Crest was designed from the ground up for deep learning. The architecture itself is a tensor-based architecture, meaning it's optimized for blocks of compute instead of operating on scalars (as would a traditional Intel CPU would).

  • Tensor-based architecture
    • Nervana Engine
  • Flexpoint number format
  • No caches
    • Software explicitly manages all on-chip memory
  • HBM2 memory
    • 32 GiB of in-package memory
    • 8 Tbit/s bandwidth
  • 12 x Inter-Chip Links (ICL)
    • bi-directional high-bandwidth direct chip-to-chip interconnect
    • 100 GB/s (1,200 GB/s aggregate)

This list is incomplete; you can help by expanding it.

Block Diagram[edit]

Chip[edit]

knights crest chip block diagram.svg

Processing Cluster[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Memory Hierarchy[edit]

  • 32 GiB on-package HBM2
    • 1 TiB/s

Die[edit]

Nervana stated that Lake Crest is "near-reticle size" implying the die size is likely around the 650-750 mm².

Additional Shots[edit]

  • Lake Crest Accelerator PCIe card (internal view)

Bibliography[edit]

  • Rao, N. (2016, November). Pathfinding and Hardware Deep Dive. 2016 AI Day, San Francisco.
  • Rao, N. (2018, May). Keynote presentation. 2018 AI DevCon, San Francisco.
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codenameLake Crest +
designerNervana +
first launchedNovember 17, 2016 +
full page namenervana/microarchitectures/lake crest +
instance ofmicroarchitecture +
manufacturerTSMC +
nameLake Crest +
process28 nm (0.028 μm, 2.8e-5 mm) +