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Difference between revisions of "intel/xeon gold/5118"
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|release price=$1273.00 | |release price=$1273.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=5100 |
|locked=Yes | |locked=Yes | ||
|frequency=2,300 MHz | |frequency=2,300 MHz | ||
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|core count=12 | |core count=12 | ||
|thread count=24 | |thread count=24 | ||
+ | |max memory=768 GiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=105 W | |tdp=105 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
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|dts min=0 °C | |dts min=0 °C | ||
|dts max=93 °C | |dts max=93 °C | ||
− | |package | + | |package name 1=intel,fclga_3647 |
+ | |successor=Xeon Gold 5218 | ||
+ | |successor link=intel/xeon_gold/5218 | ||
}} | }} | ||
'''Xeon Gold 5118''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5118, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.3 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 3.2 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. | '''Xeon Gold 5118''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5118, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.3 GHz with a TDP of 105 W and a {{intel|turbo boost}} frequency of up to 3.2 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. |
Latest revision as of 23:43, 28 December 2019
Edit Values | |
Xeon Gold 5118 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 5118 |
Part Number | CD8067303536100 |
S-Spec | SR3GF QMXH (QS) |
Market | Server |
Introduction | July 11, 2017 (announced) July 11, 2017 (launched) |
Release Price | $1273.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 5100 |
Locked | Yes |
Frequency | 2,300 MHz |
Turbo Frequency | 3,200 MHz (1 core) |
Clock multiplier | 23 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | M0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 105 W |
Tcase | 0 °C – 81 °C |
TDTS | 0 °C – 93 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 5118 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 5118, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 1 AVX-512 FMA unit as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.3 GHz with a TDP of 105 W and a turbo boost frequency of up to 3.2 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 2,300 MHz | 3,200 MHz | 3,200 MHz | 3,000 MHz | 3,000 MHz | 2,900 MHz | 2,900 MHz | 2,900 MHz | 2,900 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz |
AVX2 | 1,900 MHz | 3,100 MHz | 3,100 MHz | 2,900 MHz | 2,900 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,600 MHz | 2,300 MHz | 2,300 MHz | 2,300 MHz | 2,300 MHz |
AVX512 | 1,200 MHz | 2,900 MHz | 2,900 MHz | 2,400 MHz | 2,400 MHz | 1,800 MHz | 1,800 MHz | 1,800 MHz | 1,800 MHz | 1,600 MHz | 1,600 MHz | 1,600 MHz | 1,600 MHz |
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-09-30 22:55:00-0400
Chips: 2, Cores: 24, Threads: 24
Tested: 2017-09-30 22:55:00-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)
System: Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)
SPECspeed2017_fp_base: 82.7
SPECspeed2017_fp_peak: 83.8
Test: SPEC CPU2017
Tested: 2017-09-30 17:05:03-0400
Chips: 2, Cores: 24, Threads: 24
Tested: 2017-09-30 17:05:03-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: Cisco Systems
System: Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)
System: Cisco UCS B200 M5 (Intel Xeon Gold 5118, 2.30GHz)
SPECspeed2017_int_base: 7.62
SPECspeed2017_int_peak: 7.81
Facts about "Xeon Gold 5118 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5118 - Intel#io +, Xeon Gold 5118 - Intel + and Xeon Gold 5118 - Intel + |
base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 23 + |
core count | 12 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | M0 + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Gold + |
first announced | July 11, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon gold/5118 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) + |
ldate | July 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 354.15 K (81 °C, 177.8 °F, 637.47 °R) + |
max cpu count | 4 + |
max dts temperature | 93 °C + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 5118 + |
name | Xeon Gold 5118 + |
package | FCLGA-3647 + |
part number | CD8067303536100 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,273.00 (€ 1,145.70, £ 1,031.13, ¥ 131,539.09) + |
s-spec | SR3GF + |
s-spec (qs) | QMXH + |
series | 5100 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2400 + |
tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
technology | CMOS + |
thread count | 24 + |
turbo frequency (1 core) | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |