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Difference between revisions of "intel/xeon w/w-2145"
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− | '''W-2145''' is a {{arch|64}} [[ | + | {{intel title|Xeon W-2145}} |
+ | {{chip | ||
+ | |name=Xeon W-2145 | ||
+ | |image=intel skylake w (front).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=W-2145 | ||
+ | |part number=CD8067303533601 | ||
+ | |s-spec=SR3LQ | ||
+ | |market=Workstation | ||
+ | |first announced=August 29, 2017 | ||
+ | |first launched=August 29, 2017 | ||
+ | |release price (tray)=$1113.00 | ||
+ | |family=Xeon W | ||
+ | |series=W-2000 | ||
+ | |locked=Yes | ||
+ | |frequency=3,700 MHz | ||
+ | |turbo frequency1=4,500 MHz | ||
+ | |turbo frequency2=4,500 MHz | ||
+ | |turbo frequency3=4,300 MHz | ||
+ | |turbo frequency4=4,300 MHz | ||
+ | |turbo frequency5=4,300 MHz | ||
+ | |turbo frequency6=4,300 MHz | ||
+ | |turbo frequency7=4,300 MHz | ||
+ | |turbo frequency8=4,300 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=37 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Skylake (server) | ||
+ | |platform=Basin Falls | ||
+ | |core name=Skylake W | ||
+ | |core family=6 | ||
+ | |core stepping=U0 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=8 | ||
+ | |thread count=16 | ||
+ | |max cpus=1 | ||
+ | |max memory=512 GiB | ||
+ | |tdp=140 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=70 °C | ||
+ | |package name 1=intel,fclga_2066 | ||
+ | }} | ||
+ | '''W-2145''' is a {{arch|64}} [[octa-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at 3.7 GHz with a [[TDP]] of 140 W and a {{intel|turbo boost}} frequency of up to 4.5 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=512 KiB | ||
+ | |l1i cache=256 KiB | ||
+ | |l1i break=8x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=256 KiB | ||
+ | |l1d break=8x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=8 MiB | ||
+ | |l2 break=8x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=11 MiB | ||
+ | |l3 break=8x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=512 GiB | ||
+ | |controllers=2 | ||
+ | |channels=4 | ||
+ | |max bandwidth=79.47 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |pae=46 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=48 | ||
+ | |pcie config=x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |avx512units=2 | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=Yes | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=Yes | ||
+ | |sgx=No | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |intqat=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=3,700 MHz | ||
+ | |freq_1=4,500 MHz | ||
+ | |freq_2=4,500 MHz | ||
+ | |freq_3=4,300 MHz | ||
+ | |freq_4=4,300 MHz | ||
+ | |freq_5=4,300 MHz | ||
+ | |freq_6=4,300 MHz | ||
+ | |freq_7=4,300 MHz | ||
+ | |freq_8=4,300 MHz | ||
+ | |freq_avx2_1=4,000 MHz | ||
+ | |freq_avx2_2=4,000 MHz | ||
+ | |freq_avx2_3=3,900 MHz | ||
+ | |freq_avx2_4=3,900 MHz | ||
+ | |freq_avx2_5=3,900 MHz | ||
+ | |freq_avx2_6=3,900 MHz | ||
+ | |freq_avx2_7=3,900 MHz | ||
+ | |freq_avx2_8=3,900 MHz | ||
+ | |freq_avx512_1=4,000 MHz | ||
+ | |freq_avx512_2=4,000 MHz | ||
+ | |freq_avx512_3=3,800 MHz | ||
+ | |freq_avx512_4=3,800 MHz | ||
+ | |freq_avx512_5=3,600 MHz | ||
+ | |freq_avx512_6=3,600 MHz | ||
+ | |freq_avx512_7=3,600 MHz | ||
+ | |freq_avx512_8=3,600 MHz | ||
+ | }} |
Latest revision as of 17:07, 14 May 2019
Edit Values | |
Xeon W-2145 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | W-2145 |
Part Number | CD8067303533601 |
S-Spec | SR3LQ |
Market | Workstation |
Introduction | August 29, 2017 (announced) August 29, 2017 (launched) |
Release Price | $1113.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon W |
Series | W-2000 |
Locked | Yes |
Frequency | 3,700 MHz |
Turbo Frequency | 4,500 MHz (1 core), 4,500 MHz (2 cores), 4,300 MHz (3 cores), 4,300 MHz (4 cores), 4,300 MHz (5 cores), 4,300 MHz (6 cores), 4,300 MHz (7 cores), 4,300 MHz (8 cores) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 37 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Basin Falls |
Core Name | Skylake W |
Core Family | 6 |
Core Stepping | U0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 512 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 140 W |
Tcase | 0 °C – 70 °C |
Packaging | |
Package | FCLGA-2066 (LGA) |
Dimension | 52.5 mm × 45 mm |
Pitch | 1.016 mm |
Contacts | 2066 |
Socket | Socket R4 |
W-2145 is a 64-bit octa-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 3.7 GHz with a TDP of 140 W and a turbo boost frequency of up to 4.5 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||
---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
Normal | 3,700 MHz | 4,500 MHz | 4,500 MHz | 4,300 MHz | 4,300 MHz | 4,300 MHz | 4,300 MHz | 4,300 MHz | 4,300 MHz |
AVX2 | 4,000 MHz | 4,000 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz | |
AVX512 | 4,000 MHz | 4,000 MHz | 3,800 MHz | 3,800 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz |
Facts about "Xeon W-2145 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon W-2145 - Intel#pcie + |
base frequency | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 37 + |
core count | 8 + |
core family | 6 + |
core name | Skylake W + |
core stepping | U0 + |
designer | Intel + |
family | Xeon W + |
first announced | August 29, 2017 + |
first launched | August 29, 2017 + |
full page name | intel/xeon w/w-2145 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
ldate | August 29, 2017 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Workstation + |
max case temperature | 343.15 K (70 °C, 158 °F, 617.67 °R) + |
max cpu count | 1 + |
max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
max memory channels | 4 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | W-2145 + |
name | Xeon W-2145 + |
number of avx-512 execution units | 2 + |
package | FCLGA-2066 + |
part number | CD8067303533601 + |
platform | Basin Falls + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,113.00 (€ 1,001.70, £ 901.53, ¥ 115,006.29) + |
release price (tray) | $ 1,113.00 (€ 1,001.70, £ 901.53, ¥ 115,006.29) + |
s-spec | SR3LQ + |
series | W-2000 + |
smp max ways | 1 + |
socket | Socket R4 + |
supported memory type | DDR4-2666 + |
tdp | 140 W (140,000 mW, 0.188 hp, 0.14 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency (1 core) | 4,500 MHz (4.5 GHz, 4,500,000 kHz) + |
turbo frequency (2 cores) | 4,500 MHz (4.5 GHz, 4,500,000 kHz) + |
turbo frequency (3 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
turbo frequency (4 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
turbo frequency (5 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
turbo frequency (6 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
turbo frequency (7 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
turbo frequency (8 cores) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |