Difference between revisions of "intel/xeon bronze/3104"

	Edit Values
	Xeon Bronze 3104
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	3104
Part Number	BX806733104,; CD8067303562000
S-Spec	SR3GM; QN0D (QS)
Market	Server, Workstation
Introduction	July 11, 2017 (announced); July 11, 2017 (launched)
Release Price	$213.00
Shop	Amazon
	General Specs
Family	Xeon Bronze
Series	3000
Locked	Yes
Frequency	1,700 MHz
Clock multiplier	17
CPUID	0x50654
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Purley
Chipset	Lewisburg
Core Name	Skylake SP
Core Family	6
Core Stepping	U0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	6
Threads	6
Max Memory	768 GiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	2
Interconnect Rate	9.6 GT/s
	Electrical
TDP	85 W
Tcase	0 °C – 78 °C
TDTS	0 °C – 89 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647
	Succession
	Xeon Bronze 3204

Latest revision as of 22:21, 28 December 2019

Xeon Bronze 3104 is a 64-bit hexa-core x86 dual-socket entry-level server and workstation microprocessor introduced by Intel in mid-2017. The Bronze 3104, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 1.7 GHz with a TDP of 85 W, supports up 768 GiB of hexa-channel DDR4-2133 ECC memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

384 KiB

393,216 B
0.375 MiB

L1I$	192 KiB 196,608 B 0.188 MiB	6x32 KiB	8-way set associative
L1D$	192 KiB 196,608 B 0.188 MiB	6x32 KiB	8-way set associative	write-back

L2$

6 MiB

6,144 KiB
6,291,456 B
0.00586 GiB

		6x1 MiB	16-way set associative	write-back

L3$

8.25 MiB

8,448 KiB
8,650,752 B
0.00806 GiB

		6x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2133
Supports ECC	Yes
Max Mem	768 GiB
Controllers	2
Channels	6
Max Bandwidth	95.37 GiB/s 97,658.88 MiB/s 102.403 GB/s 102,402.758 MB/s 0.0931 TiB/s 0.102 TB/s
Bandwidth	Single 15.89 GiB/s Double 31.79 GiB/s Quad 63.58 GiB/s Hexa 95.37 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	48
Configs	x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
MBE Ctrl	Mode-Based Execute Control

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4	5	6
Normal	1,700 MHz	1,700 MHz	1,700 MHz	1,700 MHz	1,700 MHz	1,700 MHz	1,700 MHz
AVX2	1,300 MHz	1,300 MHz	1,300 MHz	1,300 MHz	1,300 MHz	1,300 MHz	1,300 MHz
AVX512	800 MHz	800 MHz	800 MHz	800 MHz	800 MHz	800 MHz	800 MHz

@@ Line 1: / Line 1: @@
 {{intel title|Xeon Bronze 3104}}
-{{mpu
+{{chip
 |name=Xeon Bronze 3104
 |image=skylake sp (basic).png
@@ Line 34: / Line 34: @@
 |core count=6
 |thread count=6
+|max memory=768 GiB
 |max cpus=2
-|max memory=768 GiB
+|smp interconnect=UPI
+|smp interconnect links=2
+|smp interconnect rate=9.6 GT/s
 |tdp=85 W
 |tcase min=0 °C
-|tcase max=79 °C
+|tcase max=78 °C
-|package module 1={{packages/intel/fclga-3647}}
+|dts min=0 °C
+|dts max=89 °C
+|package name 1=intel,fclga_3647
+|successor=Xeon Bronze 3204
+|successor link=intel/xeon_bronze/3204
 }}
-'''Xeon Bronze 3104''' is a {{arch|64}} [[hexa-core]] [[x86]] dual-socket entry-level server and workstation microprocessor introduced by [[Intel]] in mid-2017. The Bronze 3104, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]] sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 1.7 GHz with a TDP of 85 W, supports up 768 GiB of hexa-channel DDR4-2133 ECC memory.
+'''Xeon Bronze 3104''' is a {{arch|64}} [[hexa-core]] [[x86]] dual-socket entry-level server and workstation microprocessor introduced by [[Intel]] in mid-2017. The Bronze 3104, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]] sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 1.7 GHz with a TDP of 85 W, supports up 768 GiB of hexa-channel DDR4-2133 ECC memory.
 == Cache ==
-{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
+{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 {{cache size
 |l1 cache=384 KiB

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Bronze 3104 - Intel#io +
base frequency	1,700 MHz (1.7 GHz, 1,700,000 kHz) +
chipset	Lewisburg +
clock multiplier	17 +
core count	6 +
core family	6 +
core name	Skylake SP +
core stepping	U0 +
cpuid	0x50654 +
designer	Intel +
family	Xeon Bronze +
first announced	July 11, 2017 +
first launched	July 11, 2017 +
full page name	intel/xeon bronze/3104 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	384 KiB (393,216 B, 0.375 MiB) +
l1d$ description	8-way set associative +
l1d$ size	192 KiB (196,608 B, 0.188 MiB) +
l1i$ description	8-way set associative +
l1i$ size	192 KiB (196,608 B, 0.188 MiB) +
l2$ description	16-way set associative +
l2$ size	6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
l3$ description	11-way set associative +
l3$ size	8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) +
ldate	July 11, 2017 +
main image	+
manufacturer	Intel +
market segment	Server + and Workstation +
max case temperature	351.15 K (78 °C, 172.4 °F, 632.07 °R) +
max cpu count	2 +
max dts temperature	89 °C +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature	0 °C +
model number	3104 +
name	Xeon Bronze 3104 +
package	FCLGA-3647 +
part number	BX806733104 + and CD8067303562000 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 213.00 (€ 191.70, £ 172.53, ¥ 22,009.29) +
s-spec	SR3GM +
s-spec (qs)	QN0D +
series	3000 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	9.6 GT/s +
smp max ways	2 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2133 +
tdp	85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technology	CMOS +
thread count	6 +
word size	64 bit (8 octets, 16 nibbles) +

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