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Difference between revisions of "intel/xeon silver/4108"
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{{intel title|Xeon Silver 4108}} | {{intel title|Xeon Silver 4108}} | ||
− | {{ | + | {{chip |
|name=Xeon Silver 4108 | |name=Xeon Silver 4108 | ||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
Line 9: | Line 9: | ||
|part number 2=CD8067303561500 | |part number 2=CD8067303561500 | ||
|s-spec=SR3GJ | |s-spec=SR3GJ | ||
+ | |s-spec qs=QN0A | ||
|market=Server | |market=Server | ||
|first announced=July 11, 2017 | |first announced=July 11, 2017 | ||
Line 19: | Line 20: | ||
|turbo frequency1=3,000 MHz | |turbo frequency1=3,000 MHz | ||
|clock multiplier=18 | |clock multiplier=18 | ||
+ | |cpuid=0x50654 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake (server) |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
Line 32: | Line 34: | ||
|core count=8 | |core count=8 | ||
|thread count=16 | |thread count=16 | ||
+ | |max memory=768 GiB | ||
|max cpus=2 | |max cpus=2 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=2 | ||
+ | |smp interconnect rate=9.6 GT/s | ||
|tdp=85 W | |tdp=85 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=77 °C | |tcase max=77 °C | ||
− | |package | + | |dts min=0 °C |
+ | |dts max=90 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | |successor=Xeon Silver 4208 | ||
+ | |successor link=intel/xeon_silver/4208 | ||
}} | }} | ||
− | '''Xeon Silver 4108''' is a {{arch|64}} [[octa-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4108, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 1.8 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. | + | '''Xeon Silver 4108''' is a {{arch|64}} [[octa-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4108, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 1.8 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. |
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=512 KiB | |l1 cache=512 KiB | ||
Line 104: | Line 113: | ||
|sse42=Yes | |sse42=Yes | ||
|sse4a=No | |sse4a=No | ||
+ | |sse_gfni=No | ||
|avx=Yes | |avx=Yes | ||
+ | |avx_gfni=No | ||
|avx2=Yes | |avx2=Yes | ||
|avx512f=Yes | |avx512f=Yes | ||
Line 116: | Line 127: | ||
|avx512vbmi=No | |avx512vbmi=No | ||
|avx5124fmaps=No | |avx5124fmaps=No | ||
+ | |avx512vnni=No | ||
|avx5124vnniw=No | |avx5124vnniw=No | ||
|avx512vpopcntdq=No | |avx512vpopcntdq=No | ||
+ | |avx512gfni=No | ||
+ | |avx512vaes=No | ||
+ | |avx512vbmi2=No | ||
+ | |avx512bitalg=No | ||
+ | |avx512vpclmulqdq=No | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
Line 131: | Line 148: | ||
|clmul=Yes | |clmul=Yes | ||
|f16c=Yes | |f16c=Yes | ||
+ | |bfloat16=No | ||
|tbt1=No | |tbt1=No | ||
|tbt2=Yes | |tbt2=Yes | ||
|tbmt3=No | |tbmt3=No | ||
+ | |tvb=No | ||
|bpt=No | |bpt=No | ||
|eist=Yes | |eist=Yes | ||
Line 140: | Line 159: | ||
|fastmem=No | |fastmem=No | ||
|ivmd=Yes | |ivmd=Yes | ||
+ | |intelnodecontroller=No | ||
|intelnode=Yes | |intelnode=Yes | ||
|kpt=Yes | |kpt=Yes | ||
|ptt=Yes | |ptt=Yes | ||
+ | |intelrunsure=No | ||
|mbe=Yes | |mbe=Yes | ||
|isrt=No | |isrt=No | ||
Line 155: | Line 176: | ||
|vpro=Yes | |vpro=Yes | ||
|vtx=Yes | |vtx=Yes | ||
− | |vtd= | + | |vtd=Yes |
|ept=Yes | |ept=Yes | ||
|mpx=No | |mpx=No | ||
Line 161: | Line 182: | ||
|securekey=No | |securekey=No | ||
|osguard=No | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=No | ||
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 174: | Line 197: | ||
|sensemi=No | |sensemi=No | ||
|xfr=No | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
}} | }} | ||
Line 207: | Line 235: | ||
|freq_avx512_8=1,200 MHz | |freq_avx512_8=1,200 MHz | ||
}} | }} | ||
+ | |||
+ | == Benchmarks == | ||
+ | {{benchmarks main | ||
+ | | | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00433.html|test_timestamp=2017-10-26 18:22:55-0400|chip_count=2|core_count=16|copies_count=32|vendor=HPE|system=ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)|SPECrate2017_int_base=65.5|SPECrate2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00440.html|test_timestamp=2017-10-25 08:47:13-0400|chip_count=2|core_count=16|thread_count=16|vendor=HPE|system=ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)|SPECspeed2017_int_base=6.85|SPECspeed2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00457.html|test_timestamp=2017-10-25 12:03:49-0400|chip_count=2|core_count=16|thread_count=16|vendor=HPE|system=ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)|SPECspeed2017_fp_base=56.3|SPECspeed2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00475.html|test_timestamp=2017-10-26 08:39:40-0400|chip_count=2|core_count=16|copies_count=32|vendor=HPE|system=ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)|SPECrate2017_fp_base=77.5|SPECrate2017_fp_peak=}} | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake low core count die]] |
Latest revision as of 12:16, 29 December 2019
Edit Values | |
Xeon Silver 4108 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 4108 |
Part Number | BX806734108, CD8067303561500 |
S-Spec | SR3GJ QN0A (QS) |
Market | Server |
Introduction | July 11, 2017 (announced) July 11, 2017 (launched) |
Release Price | $417.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Silver |
Series | 4000 |
Locked | Yes |
Frequency | 1,800 MHz |
Turbo Frequency | 3,000 MHz (1 core) |
Clock multiplier | 18 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | U0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 2 |
Interconnect Rate | 9.6 GT/s |
Electrical | |
TDP | 85 W |
Tcase | 0 °C – 77 °C |
TDTS | 0 °C – 90 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Silver 4108 is a 64-bit octa-core x86 dual-socket mid-range performance server microprocessor introduced by Intel in mid-2017. The Silver 4108, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 1.8 GHz with a TDP of 85 W and a turbo boost frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||
---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
Normal | 1,800 MHz | 3,000 MHz | 3,000 MHz | 2,700 MHz | 2,700 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz | 2,100 MHz |
AVX2 | 1,400 MHz | 2,900 MHz | 2,900 MHz | 2,300 MHz | 2,300 MHz | 1,800 MHz | 1,800 MHz | 1,800 MHz | 1,800 MHz |
AVX512 | 900 MHz | 1,800 MHz | 1,800 MHz | 1,500 MHz | 1,500 MHz | 1,200 MHz | 1,200 MHz | 1,200 MHz | 1,200 MHz |
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-10-26 18:22:55-0400
Chips: 2, Cores: 16, Copies: 32
Tested: 2017-10-26 18:22:55-0400
Chips: 2, Cores: 16, Copies: 32
Vendor: HPE
System: ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)
System: ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)
SPECrate2017_int_base: 65.5
Test: SPEC CPU2017
Tested: 2017-10-25 08:47:13-0400
Chips: 2, Cores: 16, Threads: 16
Tested: 2017-10-25 08:47:13-0400
Chips: 2, Cores: 16, Threads: 16
Vendor: HPE
System: ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)
System: ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)
SPECspeed2017_int_base: 6.85
Test: SPEC CPU2017
Tested: 2017-10-25 12:03:49-0400
Chips: 2, Cores: 16, Threads: 16
Tested: 2017-10-25 12:03:49-0400
Chips: 2, Cores: 16, Threads: 16
Vendor: HPE
System: ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)
System: ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)
SPECspeed2017_fp_base: 56.3
Test: SPEC CPU2017
Tested: 2017-10-26 08:39:40-0400
Chips: 2, Cores: 16, Copies: 32
Tested: 2017-10-26 08:39:40-0400
Chips: 2, Cores: 16, Copies: 32
Vendor: HPE
System: ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)
System: ProLiant DL380 Gen10 (1.80 GHz, Intel Xeon Silver 4108)
SPECrate2017_fp_base: 77.5
Facts about "Xeon Silver 4108 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Silver 4108 - Intel#io +, Xeon Silver 4108 - Intel +, Xeon Silver 4108 - Intel +, Xeon Silver 4108 - Intel + and Xeon Silver 4108 - Intel + |
base frequency | 1,800 MHz (1.8 GHz, 1,800,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 18 + |
core count | 8 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | U0 + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Silver + |
first announced | July 11, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon silver/4108 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
ldate | July 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 350.15 K (77 °C, 170.6 °F, 630.27 °R) + |
max cpu count | 2 + |
max dts temperature | 90 °C + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 4108 + |
name | Xeon Silver 4108 + |
package | FCLGA-3647 + |
part number | BX806734108 + and CD8067303561500 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 417.00 (€ 375.30, £ 337.77, ¥ 43,088.61) + |
s-spec | SR3GJ + |
s-spec (qs) | QN0A + |
series | 4000 + |
smp interconnect | UPI + |
smp interconnect links | 2 + |
smp interconnect rate | 9.6 GT/s + |
smp max ways | 2 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2400 + |
tdp | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency (1 core) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |