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Difference between revisions of "intel/xeon gold/6136"
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{{intel title|Xeon Gold 6136}} | {{intel title|Xeon Gold 6136}} | ||
− | {{ | + | {{chip |
|name=Xeon Gold 6136 | |name=Xeon Gold 6136 | ||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
Line 8: | Line 8: | ||
|part number=CD8067303405800 | |part number=CD8067303405800 | ||
|s-spec=SR3B2 | |s-spec=SR3B2 | ||
+ | |s-spec qs=QMRX | ||
|market=Server | |market=Server | ||
|first announced=April 25, 2017 | |first announced=April 25, 2017 | ||
Line 13: | Line 14: | ||
|release price=$2460.00 | |release price=$2460.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=6100 |
|locked=Yes | |locked=Yes | ||
|frequency=3,000 MHz | |frequency=3,000 MHz | ||
Line 21: | Line 22: | ||
|bus rate=8 GT/s | |bus rate=8 GT/s | ||
|clock multiplier=30 | |clock multiplier=30 | ||
+ | |cpuid=0x50654 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake (server) |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
Line 34: | Line 36: | ||
|core count=12 | |core count=12 | ||
|thread count=24 | |thread count=24 | ||
+ | |max memory=768 GiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=150 W | |tdp=150 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=85 °C | |tcase max=85 °C | ||
− | |package | + | |dts min=0 °C |
+ | |dts max=103 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
}} | }} | ||
− | '''Xeon Gold 6136''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6136, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. | + | '''Xeon Gold 6136''' is a {{arch|64}} [[dodeca-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6136, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. |
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} |
The Xeon Gold 6136 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part. | The Xeon Gold 6136 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part. | ||
{{cache size | {{cache size | ||
Line 183: | Line 190: | ||
== Frequencies == | == Frequencies == | ||
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
− | {{frequency table}} | + | {{frequency table |
+ | |freq_base=3,000 MHz | ||
+ | |freq_1=3,700 MHz | ||
+ | |freq_2=3,700 MHz | ||
+ | |freq_3=3,600 MHz | ||
+ | |freq_4=3,600 MHz | ||
+ | |freq_5=3,600 MHz | ||
+ | |freq_6=3,600 MHz | ||
+ | |freq_7=3,600 MHz | ||
+ | |freq_8=3,600 MHz | ||
+ | |freq_9=3,600 MHz | ||
+ | |freq_10=3,600 MHz | ||
+ | |freq_11=3,600 MHz | ||
+ | |freq_12=3,600 MHz | ||
+ | |freq_avx2_base=2,600 MHz | ||
+ | |freq_avx2_1=3,600 MHz | ||
+ | |freq_avx2_2=3,600 MHz | ||
+ | |freq_avx2_3=3,400 MHz | ||
+ | |freq_avx2_4=3,400 MHz | ||
+ | |freq_avx2_5=3,300 MHz | ||
+ | |freq_avx2_6=3,300 MHz | ||
+ | |freq_avx2_7=3,300 MHz | ||
+ | |freq_avx2_8=3,300 MHz | ||
+ | |freq_avx2_9=3,300 MHz | ||
+ | |freq_avx2_10=3,300 MHz | ||
+ | |freq_avx2_11=3,300 MHz | ||
+ | |freq_avx2_12=3,300 MHz | ||
+ | |freq_avx512_base=2,100 MHz | ||
+ | |freq_avx512_1=3,500 MHz | ||
+ | |freq_avx512_2=3,500 MHz | ||
+ | |freq_avx512_3=3,300 MHz | ||
+ | |freq_avx512_4=3,300 MHz | ||
+ | |freq_avx512_5=3,100 MHz | ||
+ | |freq_avx512_6=3,100 MHz | ||
+ | |freq_avx512_7=3,100 MHz | ||
+ | |freq_avx512_8=3,100 MHz | ||
+ | |freq_avx512_9=2,700 MHz | ||
+ | |freq_avx512_10=2,700 MHz | ||
+ | |freq_avx512_11=2,700 MHz | ||
+ | |freq_avx512_12=2,700 MHz | ||
+ | }} | ||
+ | |||
+ | == Benchmarks == | ||
+ | {{benchmarks main | ||
+ | | | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00145.html|test_timestamp=2017-10-07 20:52:23-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECrate2017_fp_base=159|SPECrate2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00149.html|test_timestamp=2017-10-13 04:45:58-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECspeed2017_fp_base=103|SPECspeed2017_fp_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00155.html|test_timestamp=2017-10-13 05:57:20-0400|chip_count=2|core_count=24|thread_count=24|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECspeed2017_int_base=8.8|SPECspeed2017_int_peak=}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171017-00206.html|test_timestamp=2017-10-07 16:38:18-0400|chip_count=2|core_count=24|copies_count=48|vendor=HPE|system=ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)|SPECrate2017_int_base=149|SPECrate2017_int_peak=}} | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Latest revision as of 01:20, 29 December 2019
Edit Values | |
Xeon Gold 6136 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6136 |
Part Number | CD8067303405800 |
S-Spec | SR3B2 QMRX (QS) |
Market | Server |
Introduction | April 25, 2017 (announced) July 11, 2017 (launched) |
Release Price | $2460.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6100 |
Locked | Yes |
Frequency | 3,000 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 30 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 150 W |
Tcase | 0 °C – 85 °C |
TDTS | 0 °C – 103 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Gold 6136 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6136, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3 GHz with a TDP of 150 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
The Xeon Gold 6136 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 3,000 MHz | 3,700 MHz | 3,700 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz |
AVX2 | 2,600 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz |
AVX512 | 2,100 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz |
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-10-07 20:52:23-0400
Chips: 2, Cores: 24, Copies: 48
Tested: 2017-10-07 20:52:23-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECrate2017_fp_base: 159
Test: SPEC CPU2017
Tested: 2017-10-13 04:45:58-0400
Chips: 2, Cores: 24, Threads: 24
Tested: 2017-10-13 04:45:58-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECspeed2017_fp_base: 103
Test: SPEC CPU2017
Tested: 2017-10-13 05:57:20-0400
Chips: 2, Cores: 24, Threads: 24
Tested: 2017-10-13 05:57:20-0400
Chips: 2, Cores: 24, Threads: 24
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECspeed2017_int_base: 8.8
Test: SPEC CPU2017
Tested: 2017-10-07 16:38:18-0400
Chips: 2, Cores: 24, Copies: 48
Tested: 2017-10-07 16:38:18-0400
Chips: 2, Cores: 24, Copies: 48
Vendor: HPE
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
System: ProLiant DL360 Gen10 (3.00 GHz, Intel Xeon Gold 6136)
SPECrate2017_int_base: 149
Facts about "Xeon Gold 6136 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6136 - Intel#io +, Xeon Gold 6136 - Intel +, Xeon Gold 6136 - Intel +, Xeon Gold 6136 - Intel + and Xeon Gold 6136 - Intel + |
base frequency | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 30 + |
core count | 12 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | H0 + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 25, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon gold/6136 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
ldate | July 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
max cpu count | 4 + |
max dts temperature | 103 °C + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min dts temperature | 0 °C + |
model number | 6136 + |
name | Xeon Gold 6136 + |
package | FCLGA-3647 + |
part number | CD8067303405800 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 2,460.00 (€ 2,214.00, £ 1,992.60, ¥ 254,191.80) + |
s-spec | SR3B2 + |
s-spec (qs) | QMRX + |
series | 6100 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 150 W (150,000 mW, 0.201 hp, 0.15 kW) + |
technology | CMOS + |
thread count | 24 + |
turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |