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Difference between revisions of "intel/xeon gold/6128"
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{{intel title|Xeon Gold 6128}} | {{intel title|Xeon Gold 6128}} | ||
− | {{ | + | {{chip |
− | |||
|name=Xeon Gold 6128 | |name=Xeon Gold 6128 | ||
− | |||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
|designer=Intel | |designer=Intel | ||
Line 11: | Line 9: | ||
|part number 2=CD8067303592600 | |part number 2=CD8067303592600 | ||
|s-spec=SR3J4 | |s-spec=SR3J4 | ||
+ | |s-spec qs=QN34 | ||
|market=Server | |market=Server | ||
|first announced=April 25, 2017 | |first announced=April 25, 2017 | ||
Line 16: | Line 15: | ||
|release price=$1697.00 | |release price=$1697.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
− | |series= | + | |series=6100 |
|locked=Yes | |locked=Yes | ||
|frequency=3,400 MHz | |frequency=3,400 MHz | ||
Line 24: | Line 23: | ||
|bus rate=8 GT/s | |bus rate=8 GT/s | ||
|clock multiplier=34 | |clock multiplier=34 | ||
+ | |cpuid=0x50654 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake (server) |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
Line 37: | Line 37: | ||
|core count=6 | |core count=6 | ||
|thread count=12 | |thread count=12 | ||
+ | |max memory=768 GiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=115 W | |tdp=115 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=74 °C | |tcase max=74 °C | ||
− | |package | + | |dts min=0 °C |
+ | |dts max=100 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
}} | }} | ||
− | '''Xeon Gold 6128''' is a {{arch|64}} [[x86]] high | + | '''Xeon Gold 6128''' is a {{arch|64}} [[hexa-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6128, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.4 GHz with a TDP of 115 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. |
− | |||
− | |||
− | {{ | ||
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}} |
+ | The Xeon Gold 6128 features a considerably larger non-default 19.25 MiB of [[L3]], a size that would normally be found on a 14-core part. | ||
{{cache size | {{cache size | ||
|l1 cache=384 KiB | |l1 cache=384 KiB | ||
Line 64: | Line 67: | ||
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|l2 policy=write-back | |l2 policy=write-back | ||
− | |l3 cache= | + | |l3 cache=19.25 MiB |
− | |l3 break= | + | |l3 break=14x1.375 MiB |
|l3 desc=11-way set associative | |l3 desc=11-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=768 GiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=119.21 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 48 | ||
+ | | pcie config = x16 | ||
+ | | pcie config 2 = x8 | ||
+ | | pcie config 3 = x4 | ||
}} | }} | ||
Line 91: | Line 117: | ||
|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | + | |avx512f=Yes | |
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
Line 106: | Line 143: | ||
|f16c=Yes | |f16c=Yes | ||
|tbt1=No | |tbt1=No | ||
− | |tbt2= | + | |tbt2=Yes |
|tbmt3=No | |tbmt3=No | ||
|bpt=No | |bpt=No | ||
|eist=Yes | |eist=Yes | ||
− | |sst= | + | |sst=Yes |
|flex=No | |flex=No | ||
|fastmem=No | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=Yes | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=Yes | ||
+ | |mbe=Yes | ||
|isrt=No | |isrt=No | ||
|sba=No | |sba=No | ||
Line 120: | Line 164: | ||
|ipt=No | |ipt=No | ||
|tsx=Yes | |tsx=Yes | ||
− | |txt= | + | |txt=Yes |
|ht=Yes | |ht=Yes | ||
|vpro=Yes | |vpro=Yes | ||
Line 126: | Line 170: | ||
|vtd=Yes | |vtd=Yes | ||
|ept=Yes | |ept=Yes | ||
− | |mpx= | + | |mpx=No |
|sgx=No | |sgx=No | ||
|securekey=No | |securekey=No | ||
− | |osguard= | + | |osguard=No |
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 136: | Line 180: | ||
|amdvi=No | |amdvi=No | ||
|amdv=No | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
|rvi=No | |rvi=No | ||
|smt=No | |smt=No | ||
Line 141: | Line 188: | ||
|xfr=No | |xfr=No | ||
}} | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=3,400 MHz | ||
+ | |freq_1=3,700 MHz | ||
+ | |freq_2=3,700 MHz | ||
+ | |freq_3=3,700 MHz | ||
+ | |freq_4=3,700 MHz | ||
+ | |freq_5=3,700 MHz | ||
+ | |freq_6=3,700 MHz | ||
+ | |freq_avx2_base=2,900 MHz | ||
+ | |freq_avx2_1=3,600 MHz | ||
+ | |freq_avx2_2=3,600 MHz | ||
+ | |freq_avx2_3=3,600 MHz | ||
+ | |freq_avx2_4=3,600 MHz | ||
+ | |freq_avx2_5=3,600 MHz | ||
+ | |freq_avx2_6=3,600 MHz | ||
+ | |freq_avx512_base=2,300 MHz | ||
+ | |freq_avx512_1=3,500 MHz | ||
+ | |freq_avx512_2=3,500 MHz | ||
+ | |freq_avx512_3=3,300 MHz | ||
+ | |freq_avx512_4=3,300 MHz | ||
+ | |freq_avx512_5=2,900 MHz | ||
+ | |freq_avx512_6=2,900 MHz | ||
+ | }} | ||
+ | |||
+ | == Benchmarks == | ||
+ | {{benchmarks main | ||
+ | | | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00357.html|test_timestamp=2017-10-05 09:19:35-0400|chip_count=2|core_count=12|copies_count=24|vendor=HPE|system=ProLiant DL380 Gen10 (3.40 GHz, Intel Xeon Gold 6128)|SPECrate2017_fp_base=99.9|SPECrate2017_fp_peak=102}} | ||
+ | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00435.html|test_timestamp=2017-10-05 01:55:56-0400|chip_count=2|core_count=12|copies_count=24|vendor=HPE|system=ProLiant DL380 Gen10 (3.40 GHz, Intel Xeon Gold 6128)|SPECrate2017_int_base=82.7|SPECrate2017_int_peak=87.7}} | ||
+ | }} | ||
+ | |||
+ | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Latest revision as of 01:20, 29 December 2019
Edit Values | |
Xeon Gold 6128 | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6128 |
Part Number | BX806736128, CD8067303592600 |
S-Spec | SR3J4 QN34 (QS) |
Market | Server |
Introduction | April 25, 2017 (announced) July 11, 2017 (launched) |
Release Price | $1697.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6100 |
Locked | Yes |
Frequency | 3,400 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 34 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 6 |
Threads | 12 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 115 W |
Tcase | 0 °C – 74 °C |
TDTS | 0 °C – 100 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Gold 6128 is a 64-bit hexa-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6128, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.4 GHz with a TDP of 115 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache[edit]
- Main article: Skylake § Cache
The Xeon Gold 6128 features a considerably larger non-default 19.25 MiB of L3, a size that would normally be found on a 14-core part.
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||
---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | ||
Normal | 3,400 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz | 3,700 MHz |
AVX2 | 2,900 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz |
AVX512 | 2,300 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 2,900 MHz | 2,900 MHz |
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-10-05 09:19:35-0400
Chips: 2, Cores: 12, Copies: 24
Vendor: HPE
System: ProLiant DL380 Gen10 (3.40 GHz, Intel Xeon Gold 6128)
Tested: 2017-10-05 09:19:35-0400
Chips: 2, Cores: 12, Copies: 24
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL380 Gen10 (3.40 GHz, Intel Xeon Gold 6128)
SPECrate2017_fp_base: 99.9
SPECrate2017_fp_peak: 102
Test: SPEC CPU2017
Tested: 2017-10-05 01:55:56-0400
Chips: 2, Cores: 12, Copies: 24
Vendor: HPE
System: ProLiant DL380 Gen10 (3.40 GHz, Intel Xeon Gold 6128)
Tested: 2017-10-05 01:55:56-0400
Chips: 2, Cores: 12, Copies: 24
![benchmarks.svg](/w/images/thumb/b/b8/benchmarks.svg/64px-benchmarks.svg.png)
System: ProLiant DL380 Gen10 (3.40 GHz, Intel Xeon Gold 6128)
SPECrate2017_int_base: 82.7
SPECrate2017_int_peak: 87.7
Facts about "Xeon Gold 6128 - Intel"
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and OS Guard + |
has intel enhanced speedstep technology | true + |
has intel supervisor mode execution protection | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) + |
x86/has memory protection extensions | true + |