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Difference between revisions of "intel/xeon gold/6134"
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{{intel title|Xeon Gold 6134}}
 
{{intel title|Xeon Gold 6134}}
−
{{mpu
+
{{chip
−
| future              = Yes
+
|name=Xeon Gold 6134
−
| name               = Xeon Gold 6134
+
|image=skylake sp (basic).png
−
| no image           = Yes
+
|designer=Intel
−
| image              =
+
|manufacturer=Intel
−
| image size          =
+
|model number=6134
−
| caption            =  
+
|part number=BX806736134
−
| designer           = Intel
+
|part number 2=CD8067303330302
−
| manufacturer       = Intel
+
|s-spec=SR3AR
−
| model number       = 6134
+
|s-spec qs=QMRL
−
| part number         = CD8067303330302
+
|market=Server
−
| part number 1      =  
+
|first announced=April 25, 2017
−
| part number 2       =  
+
|first launched=July 11, 2017
−
| s-spec             = SR3AR
+
|release price=$2214.00
−
| s-spec 2            =  
+
|family=Xeon Gold
−
| market             = Server
+
|series=6100
−
| first announced     = April 25, 2017
+
|locked=Yes
−
| first launched     =
+
|frequency=3,200 MHz
−
| last order          =
+
|turbo frequency1=3,700 MHz
−
| last shipment      =  
+
|bus type=DMI 3.0
−
| release price       =  
+
|bus links=4
−
 
+
|bus rate=8 GT/s
−
| family             = Xeon Gold
+
|clock multiplier=32
−
| series             = 6100
+
|cpuid=0x50654
−
| locked             = Yes
+
|isa=x86-64
−
| frequency           = 3.2 GHz
+
|isa family=x86
−
| turbo frequency    =
+
|microarch=Skylake (server)
−
| turbo frequency1   =
+
|platform=Purley
−
| turbo frequency2    =
+
|chipset=Lewisburg
−
| turbo frequency3    =
+
|core name=Skylake SP
−
| turbo frequency4    =
+
|core family=6
−
| turbo frequency5    =
+
|core stepping=H0
−
| turbo frequency6    =
+
|process=14 nm
−
| turbo frequency7    =
+
|technology=CMOS
−
| turbo frequency8    =  
+
|word size=64 bit
−
| bus type           = DMI 3.0
+
|core count=8
−
| bus speed          =  
+
|thread count=16
−
| bus rate           = 8 GT/s
+
|max memory=768 GiB
−
| bus links          = 4
+
|max cpus=4
−
| clock multiplier   = 32
+
|smp interconnect=UPI
−
| cpuid               =
+
|smp interconnect links=3
−
| cpuid 2            =  
+
|smp interconnect rate=10.4 GT/s
−
 
+
|tdp=130 W
−
| isa family          = x86-64
+
|tcase min=0 °C
−
| isa                 = x86
+
|tcase max=79 °C
−
| microarch           = Skylake
+
|dts min=0 °C
−
| platform           = Purley
+
|dts max=100 °C
−
| chipset             = Lewisburg
+
|package name 1=intel,fclga_3647
−
| core name           = Skylake SP
+
|successor=Xeon Gold 6234
−
| core family         =
+
|successor link=intel/xeon_gold/6234
−
| core model          =  
 
−
| core stepping       = H0
 
−
| process             = 14 nm
 
−
| transistors        =
 
−
| technology         = CMOS
 
−
| die area            = <!-- XX mm² -->
 
−
| die width          =
 
−
| die length          =
 
−
| word size           = 64 bit
 
−
| core count         = 18
 
−
| thread count       = 36
 
−
| max cpus            = 2
 
−
| max memory         =
 
−
 
 
−
| electrical          =
 
−
| power              =
 
−
| average power      =
 
−
| idle power          =
 
−
| v core              =  
 
−
| v core tolerance    = <!-- OR ... -->
 
−
| v core min          =
 
−
| v core max         =  
 
−
| v io                =  
 
−
| v io tolerance      =  
 
−
| v io 2              = <!-- OR ... -->
 
−
| v io 3              =
 
−
| sdp                =
 
−
| tdp                 =  
 
−
| tdp typical        =
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp min           = <!-- use TJ/TC whenever possible instead -->
 
−
| temp max            =
 
−
| tjunc min          = <!-- .. °C -->
 
−
| tjunc max          =
 
−
| tcase min          =
 
−
| tcase max           =  
 
−
| tstorage min       =  
 
−
| tstorage max       =  
 
−
| tambient min        =
 
−
| tambient max        =
 
−
 
 
−
| package module 1   =
 
−
| package module 2    =  
 
−
<!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE -------------->
 
−
| packaging          = Yes
 
−
| package 0          = FCLGA-3647
 
−
| package 0 type      = LGA
 
−
| package 0 pins      = 3647
 
−
| package 0 pitch    =
 
−
| package 0 width    =
 
−
| package 0 length    =
 
−
| package 0 height    =
 
−
| socket 0            = LGA-3647
 
−
| socket 0 type      = LGA
 
 
}}
 
}}
−
'''Xeon Gold 6134''' is a {{arch|64}} [[x86]] high-performance server [[octadeca-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6134 operates at 3.2 GHz.
+
'''Xeon Gold 6134''' is a {{arch|64}} [[octa-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6134, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.2 GHz with a TDP of 130 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
−
 
 
−
 
 
−
{{unknown features}}
 
  
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
+
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 +
The Xeon Gold 6134 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part.
 
{{cache size
 
{{cache size
−
|l1 cache=1.125 MiB
+
|l1 cache=512 KiB
−
|l1i cache=576 KiB
+
|l1i cache=256 KiB
−
|l1i break=18x32 KiB
+
|l1i break=8x32 KiB
 
|l1i desc=8-way set associative
 
|l1i desc=8-way set associative
−
|l1d cache=576 KiB
+
|l1d cache=256 KiB
−
|l1d break=18x32 KiB
+
|l1d break=8x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
 
|l1d policy=write-back
 
|l1d policy=write-back
−
|l2 cache=18 MiB
+
|l2 cache=8 MiB
−
|l2 break=18x1 MiB
+
|l2 break=8x1 MiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back
Line 138: Line 79:
 
|type=DDR4-2666
 
|type=DDR4-2666
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=
+
|max mem=768 GiB
−
|controllers=1
+
|controllers=2
 
|channels=6
 
|channels=6
 
|max bandwidth=119.21 GiB/s
 
|max bandwidth=119.21 GiB/s
−
|bandwidth schan=19.89 GiB/s
+
|bandwidth schan=19.87 GiB/s
−
|bandwidth dchan=39.72 GiB/s
+
|bandwidth dchan=39.74 GiB/s
 
|bandwidth qchan=79.47 GiB/s
 
|bandwidth qchan=79.47 GiB/s
 
|bandwidth hchan=119.21 GiB/s
 
|bandwidth hchan=119.21 GiB/s
 
}}
 
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 48
 +
| pcie config        = x16
 +
| pcie config 2      = x8
 +
| pcie config 3      = x4
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=Yes
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=Yes
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=3,200 MHz
 +
|freq_1=3,700 MHz
 +
|freq_2=3,700 MHz
 +
|freq_3=3,700 MHz
 +
|freq_4=3,700 MHz
 +
|freq_5=3,700 MHz
 +
|freq_6=3,700 MHz
 +
|freq_7=3,700 MHz
 +
|freq_8=3,700 MHz
 +
|freq_avx2_base=2,700 MHz
 +
|freq_avx2_1=3,600 MHz
 +
|freq_avx2_2=3,600 MHz
 +
|freq_avx2_3=3,400 MHz
 +
|freq_avx2_4=3,400 MHz
 +
|freq_avx2_5=3,400 MHz
 +
|freq_avx2_6=3,400 MHz
 +
|freq_avx2_7=3,400 MHz
 +
|freq_avx2_8=3,400 MHz
 +
|freq_avx512_base=2,100 MHz
 +
|freq_avx512_1=3,500 MHz
 +
|freq_avx512_2=3,500 MHz
 +
|freq_avx512_3=3,300 MHz
 +
|freq_avx512_4=3,300 MHz
 +
|freq_avx512_5=2,700 MHz
 +
|freq_avx512_6=2,700 MHz
 +
|freq_avx512_7=2,700 MHz
 +
|freq_avx512_8=2,700 MHz
 +
}}
 +
 +
== Benchmarks ==
 +
{{benchmarks main
 +
|
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00322.html|test_timestamp=2017-10-29 15:10:57-0400|chip_count=2|core_count=16|copies_count=32|vendor=HPE|system=ProLiant DL360 Gen10 (3.20 GHz, Intel Xeon Gold 6134)|SPECrate2017_int_base=106|SPECrate2017_int_peak=}}
 +
{{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00325.html|test_timestamp=2017-10-30 01:48:09-0400|chip_count=2|core_count=16|copies_count=32|vendor=HPE|system=ProLiant DL360 Gen10 (3.20 GHz, Intel Xeon Gold 6134)|SPECrate2017_fp_base=123|SPECrate2017_fp_peak=}}
 +
}}
 +
 +
[[Category:microprocessor models by intel based on skylake extreme core count die]]

Latest revision as of 00:20, 29 December 2019

Edit Values
Xeon Gold 6134
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6134
Part NumberBX806736134,
CD8067303330302
S-SpecSR3AR
QMRL (QS)
MarketServer
IntroductionApril 25, 2017 (announced)
July 11, 2017 (launched)
Release Price$2214.00
ShopAmazon
General Specs
FamilyXeon Gold
Series6100
LockedYes
Frequency3,200 MHz
Turbo Frequency3,700 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier32
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformPurley
ChipsetLewisburg
Core NameSkylake SP
Core Family6
Core SteppingH0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads16
Max Memory768 GiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP130 W
Tcase0 °C – 79 °C
TDTS0 °C – 100 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 6134 is a 64-bit octa-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6134, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.2 GHz with a TDP of 130 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache[edit]

Main article: Skylake § Cache

The Xeon Gold 6134 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
  18x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678
Normal3,200 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz3,700 MHz
AVX22,700 MHz3,600 MHz3,600 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz
AVX5122,100 MHz3,500 MHz3,500 MHz3,300 MHz3,300 MHz2,700 MHz2,700 MHz2,700 MHz2,700 MHz

Benchmarks[edit]

[Edit Benchmarks]

Test: SPEC CPU2017
Tested: 2017-10-29 15:10:57-0400
Chips: 2, Cores: 16, Copies: 32
benchmarks.svg
Vendor: HPE
System: ProLiant DL360 Gen10 (3.20 GHz, Intel Xeon Gold 6134)
SPECrate2017_int_base: 106
Test: SPEC CPU2017
Tested: 2017-10-30 01:48:09-0400
Chips: 2, Cores: 16, Copies: 32
benchmarks.svg
Vendor: HPE
System: ProLiant DL360 Gen10 (3.20 GHz, Intel Xeon Gold 6134)
SPECrate2017_fp_base: 123
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6134&oldid=95135"
Facts about "Xeon Gold 6134 - Intel"
RDF feed
has ecc memory supporttrue +
l1$ size1,152 KiB (1,179,648 B, 1.125 MiB) +
l1d$ description8-way set associative +
l1d$ size576 KiB (589,824 B, 0.563 MiB) +
l1i$ description8-way set associative +
l1i$ size576 KiB (589,824 B, 0.563 MiB) +
l2$ description16-way set associative +
l2$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
l3$ description11-way set associative +
l3$ size24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
supported memory typeDDR4-2666 +