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Difference between revisions of "intel/chipsets/poulsbo"
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| image = poulsbo sch.png | | image = poulsbo sch.png | ||
| image size = | | image size = | ||
| − | | image 2 = | + | | caption = Original package |
| + | | image 2 = poulsbo sch (large package).png | ||
| image 2 size = | | image 2 size = | ||
| + | | caption 2 = A larger package was introduced in early 2009 | ||
| developer = Intel | | developer = Intel | ||
| developer 2 = Imagination Technologies | | developer 2 = Imagination Technologies | ||
| manufacturer = Intel | | manufacturer = Intel | ||
| − | | first announced = | + | | first announced = April 18, 2007 |
| − | | first launched = | + | | first launched = March 2, 2008 |
| proc = 0.13 μm | | proc = 0.13 μm | ||
| tech = CMOS | | tech = CMOS | ||
| Line 20: | Line 22: | ||
| socket = | | socket = | ||
| − | | succession = | + | | succession = Yes |
| predecessor = | | predecessor = | ||
| predecessor link = | | predecessor link = | ||
| − | | successor = | + | | successor = Langwell |
| − | | successor link = | + | | successor link = intel/chipsets/langwell |
}} | }} | ||
'''Poulsbo''' is a chipset for [[Intel]]'s first generation of {{intel|Atom}} processors based on the {{intel|Bonnell|l=arch}} microarchitecture. | '''Poulsbo''' is a chipset for [[Intel]]'s first generation of {{intel|Atom}} processors based on the {{intel|Bonnell|l=arch}} microarchitecture. | ||
==Overview == | ==Overview == | ||
| − | {{ | + | [[File:Poulsbo lrg and sm.png|thumb|right|Comparison between the two Poulsbo packages.]] |
| + | The Poulsbo chipset, part of the {{intel|Menlow|l=platform}}, offers the memory controller along with the much of the southbridge. Unlike all previous [[front-side bus]] signaling logic which used [[gunning transceiver logic|GTL]], to allow for more power saving, Poulsbo became the first chipset to support CMOS signaling as well. Such functionality was only offered by the {{intel|Silverthorne|l=core}}-based processors. In 2009 Intel released a second variant of Poulsbo in a larger [[package]]. | ||
| + | |||
| + | == Features == | ||
| + | * Intel {{intel|GMA 500}} GPU | ||
| + | ** Licensed Imagination Technologies {{imgtec|PowerVR SGX 535}} graphics core + {{imgtec|PowerVR VXD370}} H.264/MPEG-4 AVC playback | ||
| + | {{expand section}} | ||
{{clear}} | {{clear}} | ||
| + | |||
== Die Shot == | == Die Shot == | ||
* [[0.13 μm process]] | * [[0.13 μm process]] | ||
| − | [[File:poulsbo die.png| | + | * 22 mm x 22 mm package |
| + | [[File:poulsbo die.png|1200px]] | ||
| + | |||
| + | |||
| + | [[File:poulsbo die (annotated).png|1200px]] | ||
| + | |||
| + | == Documents == | ||
| + | * [[:File:poulsbo product brief.pdf|Intel Poulsbo product brief]] | ||
Latest revision as of 18:52, 3 April 2017
| Poulsbo | |
| |
| Original package | |
.png)
| |
| A larger package was introduced in early 2009 | |
| Developer | Intel, Imagination Technologies |
| Manufacturer | Intel |
| Introduction | April 18, 2007 (announced) March 2, 2008 (launch) |
| Process | 0.13 μm 130 nm
1.3e-4 mm |
| Technology | CMOS, GTL |
| Bus type | FSB |
| Bus speed | 0.533 GHz 533 MHz
533,000 kHz |
| Succession | |
| → | |
| Langwell | |
Poulsbo is a chipset for Intel's first generation of Atom processors based on the Bonnell microarchitecture.
Contents
Overview[edit]
The Poulsbo chipset, part of the Menlow, offers the memory controller along with the much of the southbridge. Unlike all previous front-side bus signaling logic which used GTL, to allow for more power saving, Poulsbo became the first chipset to support CMOS signaling as well. Such functionality was only offered by the Silverthorne-based processors. In 2009 Intel released a second variant of Poulsbo in a larger package.
Features[edit]
- Intel GMA 500 GPU
- Licensed Imagination Technologies PowerVR SGX 535 graphics core + PowerVR VXD370 H.264/MPEG-4 AVC playback
 |
This section requires expansion; you can help adding the missing info. |
Die Shot[edit]
- 0.13 μm process
- 22 mm x 22 mm package
.png)
Documents[edit]
Facts about "Poulsbo - Chipsets - Intel"
| bus speed | 533 MHz (0.533 GHz, 533,000 kHz) + |
| bus type | FSB + |
| designer | Intel + and Imagination Technologies + |
| first announced | April 18, 2007 + |
| first launched | March 2, 2008 + |
| instance of | chipset + |
| manufacturer | Intel + |
| name | Poulsbo + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| technology | CMOS + and GTL + |