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| image            = poulsbo sch.png
 
| image            = poulsbo sch.png
 
| image size        =  
 
| image size        =  
| image 2          =  
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| caption          = Original package
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| image 2          = poulsbo sch (large package).png
 
| image 2 size      =  
 
| image 2 size      =  
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| caption 2        = A larger package was introduced in early 2009
 
| developer        = Intel
 
| developer        = Intel
 
| developer 2      = Imagination Technologies
 
| developer 2      = Imagination Technologies
 
| manufacturer      = Intel
 
| manufacturer      = Intel
| first announced  = March 2, 2008
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| first announced  = April 18, 2007
| first launched    =  
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| first launched    = March 2, 2008
 
| proc              = 0.13 μm
 
| proc              = 0.13 μm
 
| tech              = CMOS
 
| tech              = CMOS
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| socket            =  
 
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| succession      = Yes
 
| predecessor      =  
 
| predecessor      =  
 
| predecessor link =  
 
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| successor        =  
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| successor        = Langwell
| successor link  =  
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| successor link  = intel/chipsets/langwell
 
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'''Poulsbo''' is a chipset for [[Intel]]'s first generation of {{intel|Atom}} processors based on the {{intel|Bonnell|l=arch}} microarchitecture.
 
'''Poulsbo''' is a chipset for [[Intel]]'s first generation of {{intel|Atom}} processors based on the {{intel|Bonnell|l=arch}} microarchitecture.
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==Overview ==
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[[File:Poulsbo lrg and sm.png|thumb|right|Comparison between the two Poulsbo packages.]]
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The Poulsbo chipset, part of the {{intel|Menlow|l=platform}}, offers the memory controller along with the much of the southbridge. Unlike all previous [[front-side bus]] signaling logic which used [[gunning transceiver logic|GTL]], to allow for more power saving, Poulsbo became the first chipset to support CMOS signaling as well. Such functionality was only offered by the {{intel|Silverthorne|l=core}}-based processors. In 2009 Intel released a second variant of Poulsbo in a larger [[package]].
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== Features ==
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* Intel {{intel|GMA 500}} GPU
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** Licensed Imagination Technologies {{imgtec|PowerVR SGX 535}} graphics core + {{imgtec|PowerVR VXD370}} H.264/MPEG-4 AVC playback
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{{expand section}}
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 +
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{{clear}}
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== Die Shot ==
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* [[0.13 μm process]]
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* 22 mm x 22 mm package
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[[File:poulsbo die.png|1200px]]
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 +
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[[File:poulsbo die (annotated).png|1200px]]
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== Documents ==
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* [[:File:poulsbo product brief.pdf|Intel Poulsbo product brief]]

Latest revision as of 18:52, 3 April 2017

Poulsbo
poulsbo sch.png
Original package
poulsbo sch (large package).png
A larger package was introduced in early 2009
Developer Intel, Imagination Technologies
Manufacturer Intel
Introduction April 18, 2007 (announced)
March 2, 2008 (launch)
Process 0.13 μm
130 nm
1.3e-4 mm
Technology CMOS, GTL
Bus type FSB
Bus speed
0.533 GHz
533,000 kHz
533 MHz
Succession
Langwell

Poulsbo is a chipset for Intel's first generation of Atom processors based on the Bonnell microarchitecture.

Overview[edit]

Comparison between the two Poulsbo packages.

The Poulsbo chipset, part of the Menlow, offers the memory controller along with the much of the southbridge. Unlike all previous front-side bus signaling logic which used GTL, to allow for more power saving, Poulsbo became the first chipset to support CMOS signaling as well. Such functionality was only offered by the Silverthorne-based processors. In 2009 Intel released a second variant of Poulsbo in a larger package.

Features[edit]

New text document.svg This section requires expansion; you can help adding the missing info.


Die Shot[edit]

poulsbo die.png


poulsbo die (annotated).png

Documents[edit]

bus speed533 MHz (0.533 GHz, 533,000 kHz) +
bus typeFSB +
designerIntel + and Imagination Technologies +
first announcedMarch 2, 2008 +
instance ofchipset +
manufacturerIntel +
namePoulsbo +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyCMOS + and GTL +