From WikiChip
Difference between revisions of "ibm/microarchitectures/power8"
< ibm

(→‎Octa-Core)
 
(5 intermediate revisions by one other user not shown)
Line 35: Line 35:
 
| extension N  =  
 
| extension N  =  
  
−
| cache        =  
+
| cache        = Yes
−
| l1i          =  
+
| l1i          = 32 KiB
−
| l1i per      =  
+
| l1i per      = core
−
| l1i desc      =
+
| l1i desc      = 8-way set associative
−
| l1d          =  
+
| l1d          = 64 KiB
−
| l1d per      =  
+
| l1d per      = core
−
| l1d desc      =
+
| l1d desc      = 8-way set associative
−
| l2            =  
+
| l2            = 512 KiB
−
| l2 per        =  
+
| l2 per        = core
 
| l2 desc      =  
 
| l2 desc      =  
−
| l3            =  
+
| l3            = 8 MiB
−
| l3 per        =  
+
| l3 per        = core
 
| l3 desc      =  
 
| l3 desc      =  
 +
| l4            = 128 MiB
 +
| l4 per        = chip
 +
| l4 desc      =
  
 
| core names      = <!-- Yes if specify -->
 
| core names      = <!-- Yes if specify -->
Line 57: Line 60:
 
| predecessor      = POWER7+
 
| predecessor      = POWER7+
 
| predecessor link = ibm/microarchitectures/power7+
 
| predecessor link = ibm/microarchitectures/power7+
−
| successor        = POWER9
+
| successor        = POWER8+
−
| successor link  = ibm/microarchitectures/power9
+
| successor link  = ibm/microarchitectures/power8+
 
}}
 
}}
 
'''POWER8''' is the [[Power]] microarchitecture for [[IBM]]'s family of {{ibm|POWER8}} processors that was introduced in [[2014]]. POWER8 is the successor to {{\\|POWER7+}}.
 
'''POWER8''' is the [[Power]] microarchitecture for [[IBM]]'s family of {{ibm|POWER8}} processors that was introduced in [[2014]]. POWER8 is the successor to {{\\|POWER7+}}.
 +
 +
== Architectures ==
 +
=== Key changes from {{\\|POWER7}}/{{\\|POWER7+|+}} ===
 +
{{empty section}}
 +
 +
== Die ==
 +
=== Dodeca-Core ===
 +
* [[Dodeca-Core]]
 +
* IBM's [[22 nm process|22 nm SOI process]]
 +
* 15 metal layers
 +
* 4,200,000,000 transistors
 +
* 649 mm² die size
 +
: [[File:power8 die shot (12-core).png|750px]]
 +
 +
 +
: [[File:power8 die shot (12-core)(annotated).png|750px]]
 +
 +
=== Hexa-Core ===
 +
* [[hexa-core]]
 +
* IBM's [[22 nm process|22 nm SOI process]]
 +
* 15 metal layers
 +
* 362 mm² die size
 +
 +
: ?die shot?
 +
 +
: [[File:power8 die shot (6-core)(annotated).png|450px]]

Latest revision as of 14:30, 3 September 2017

Edit Values
POWER8 µarch
General Info
Arch TypeCPU
DesignerIBM
ManufacturerIBM
IntroductionAugust, 2013
Phase-outJune, 2014
Process22 nm
Core Configs4, 6, 8, 10, 12
Pipeline
TypeSuperscalar
SpeculativeYes
Reg RenamingYes
Stages15-23
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache64 KiB/core
8-way set associative
L2 Cache512 KiB/core
L3 Cache8 MiB/core
L4 Cache128 MiB/chip
Succession

POWER8 is the Power microarchitecture for IBM's family of POWER8 processors that was introduced in 2014. POWER8 is the successor to POWER7+.

Architectures[edit]

Key changes from POWER7/+[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die[edit]

Dodeca-Core[edit]

power8 die shot (12-core).png


power8 die shot (12-core)(annotated).png

Hexa-Core[edit]

 ?die shot?
power8 die shot (6-core)(annotated).png
Retrieved from "https://en.wikichip.org/w/index.php?title=ibm/microarchitectures/power8&oldid=63265"
Facts about "POWER8 - Microarchitectures - IBM"
RDF feed
codenamePOWER8 +
core count4 +, 6 +, 8 +, 10 + and 12 +
designerIBM +
first launchedAugust 2013 +
full page nameibm/microarchitectures/power8 +
instance ofmicroarchitecture +
manufacturerIBM +
microarchitecture typeCPU +
namePOWER8 +
phase-outJune 2014 +
pipeline stages (max)23 +
pipeline stages (min)15 +
process22 nm (0.022 μm, 2.2e-5 mm) +