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Difference between revisions of "mediatek/helio/mt6795t"
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(Created page with "{{mediatek title|Helio X10 (MT6795T)}} '''Helio X10''' ('''MT6795T''') is a {{arch|64}} octa-core ARM LTE system on a chip designed by MediaTek and introduced...")
 
(I have added one more model that i am using on this chip)
 
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{{mediatek title|Helio X10 (MT6795T)}}
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{{mediatek title|Helio X10 T (MT6795T)}}
−
'''Helio X10''' ('''MT6795T''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in late-[[2014]]. This SoC, which is manufactured on TSMC's [[28 nm process]], operates at up to 2.2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 4.
+
{{chip
 +
| name                = MediaTek Helio X10 T
 +
| no image            = yes
 +
| image              =
 +
| image size          =
 +
| caption            =
 +
| designer            = MediaTek
 +
| designer 2          = ARM Holdings
 +
| manufacturer        = TSMC
 +
| model number        = Helio X10 T
 +
| part number        = MT6795T
 +
| part number 2      = MTK6795T
 +
| market              = Mobile
 +
| market 2            = Embedded
 +
| first announced    = July 15, 2014
 +
| first launched      = March 27, 2015
 +
| last order          =
 +
| last shipment      =
 +
| release price      =
 +
 
 +
| family              = Helio
 +
| series              = Helio X
 +
| locked              =
 +
| frequency          = 2,200 MHz
 +
| bus type            = AMBA 4 AXI
 +
| bus speed          =
 +
| bus rate            =
 +
| bus links          =
 +
| clock multiplier    =
 +
 
 +
| isa family          = ARM
 +
| isa                = ARMv8
 +
| microarch          = Cortex-A53
 +
| platform            =
 +
| chipset            =
 +
| core name          = Cortex-A53
 +
| core family        =
 +
| core model          =
 +
| core stepping      =
 +
| process            = 28 nm
 +
| transistors        =
 +
| technology          = CMOS
 +
| die area            = <!-- XX mm² -->
 +
| die width          =
 +
| die length          =
 +
| word size          = 64 bit
 +
| core count          = 8
 +
| thread count        = 8
 +
| max cpus            = 1
 +
| max memory          = 4 GiB
 +
 
 +
 
 +
| power              =
 +
| v core              = 1 V
 +
| v core tolerance    =
 +
| v io                = 1.8 V
 +
| v io 2              = 2.8 V
 +
| v io 3              = 3.3 V
 +
| sdp                =
 +
| tdp                =
 +
| tdp typical        =
 +
| ctdp down          =
 +
| ctdp down frequency =
 +
| ctdp up            =
 +
| ctdp up frequency  =
 +
| temp min            = -20 °C
 +
| temp max            = 80 °C
 +
| tjunc min          =
 +
| tjunc max          = 125 °C
 +
| tcase min          =
 +
| tcase max          =
 +
| tstorage min        = 0 °C
 +
| tstorage max        = 125 °C
 +
| tambient min        =
 +
| tambient max        =
 +
 
 +
| packaging          = Yes
 +
| package 0          = MWPOP-1108
 +
| package 0 type      = MWPOP
 +
| package 0 pins      = 1108
 +
| package 0 pitch    = 0.4 mm
 +
| package 0 width    = 14 mm
 +
| package 0 length    = 14 mm
 +
| package 0 height    = 0.78 mm
 +
}}
 +
'''Helio X10 T''' ('''MT6795T'''; T for ''turbo'') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in early-[[2015]]. This SoC, which incorporates eight {{armh|Cortex-A53}} cores and is manufactured on TSMC's [[28 nm process]], operates at up to 2.2 GHz and supports dual-channel LPDDR3-1866. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 4. This "turbo" variant of the X10 operates at 10% higher frequency.
 +
 
 +
This SoC is made of 2 clusters of 4-core each ({{armh|Cortex-A53}}) linked together via a {{armh|CCI-400}}, a {{armh|NEON}} engine, and {{armh|Cortex-R4}} core for the second MCU subsystem.
 +
 
 +
== Cache ==
 +
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}}
 +
{{cache size
 +
|l1 cache = 512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=2-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=2 MiB
 +
|l2 break=2x1 MiB
 +
|l2 desc=16-way set associative
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR3-1866
 +
|ecc=No
 +
|max mem=4 GiB
 +
|controllers=1
 +
|channels=2
 +
|width=32 bit
 +
|max bandwidth=13.91 GiB/s
 +
|bandwidth schan=6.95 GiB/s
 +
|bandwidth dchan=13.91 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions
 +
|usb revision=2.0
 +
|usb revision 2=3.0
 +
|usb ports=8
 +
|uart=4
 +
|gp io=Yes
 +
}}
 +
 
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = PowerVR G6200
 +
| device id          =
 +
| designer            = Imagination Technologies
 +
| execution units    =
 +
| max displays        = 2
 +
| max memory          =
 +
| frequency          = 700 MHz
 +
 
 +
| output dsi          = Yes
 +
 
 +
| max res dsi        = 2560x1600
 +
 
 +
| direct3d ver        = 10.0
 +
| opencl ver          = 1.2
 +
| opengl ver          = 3.2
 +
| opengl es ver      = 3.1
 +
| vulkan ver          = 1.0
 +
}}
 +
 
 +
* OpenGL ES 3.0 3D graphic accelerator capable of processing 175M tri/sec and 2,800M pixel/sec  @ 700 MHz
 +
* OpenVG 1.1 vector graphics accelerator
 +
 
 +
== Wireless ==
 +
{{wireless links
 +
| 2g                = Yes
 +
| csd              = Yes
 +
| gsm              = Yes
 +
| gprs              = Yes
 +
| edge              = Yes
 +
| cdmaone          =
 +
| is-95a            =
 +
| is-95b            =
 +
| 3g                = Yes
 +
| cdma2000          =
 +
| cdma2000 1x      =
 +
| cdma2000 1xev-do  =
 +
| cdma2000 1x adv  =
 +
| umts              = Yes
 +
| wcdma            = 
 +
| td-scdma          = Yes
 +
| dc-hsdpa          = Yes
 +
| hsdpa            =
 +
| hsupa            = Yes
 +
| 4g                = Yes
 +
| lte a            = Yes
 +
| e-utran          = Yes
 +
| ue cat            = 4
 +
}}
 +
 
 +
== Image ==
 +
* Integrated image signal processor supports 20 MP
 +
* Supports image stabilization
 +
* Supports video stabilization
 +
* Supports noise reduction
 +
* Supports lens shading correction
 +
* Supports AE/AWB/AF
 +
* Supports edge enhancement
 +
* Supports face detection and visual tracking
 +
* Hardware JPEG encoder
 +
 
 +
== Video ==
 +
* HEVC decoder 4k2k @ 30fps
 +
* H.264 decoder (30fps/40Mbps)
 +
* Sorenson H.263/H.263 decoder (1080p @ 60fps/40Mbps)
 +
* MPEG-4 SP/ASP decoder (1080p @ 60fps/40Mbps)
 +
* DIVX4/DIVX5/DIVX6/DIVX HD/XVID decoder  (1080p @ 60fps/40Mbps)
 +
* VP8 / VC-1 decoders
 +
* MPEG-4 / H.263 / H.264 / HEVC encoders
 +
 
 +
== Audio ==
 +
* Audio content sampling rates 8kHz to 192kHz
 +
* Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
 +
* I2S, PCM
 +
* Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
 +
* Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
 +
* 7.1 channel MHL output
 +
 
 +
== Utilizing devices ==
 +
* [[used by::Meizu MX5]]
 +
* [[used by::LeEco Le 1s]]
 +
* [[used by::Xiaomi Redmi Note 2]]
 +
* [[used by::HTC One X9]]
 +
* [[used by::HTC One M9+]]
 +
* [[used by::HTC One ME]]
 +
 
 +
{{expand list}}

Latest revision as of 08:36, 22 August 2018

Edit Values
MediaTek Helio X10 T
General Info
DesignerMediaTek,
ARM Holdings
ManufacturerTSMC
Model NumberHelio X10 T
Part NumberMT6795T,
MTK6795T
MarketMobile, Embedded
IntroductionJuly 15, 2014 (announced)
March 27, 2015 (launched)
General Specs
FamilyHelio
SeriesHelio X
Frequency2,200 MHz
Bus typeAMBA 4 AXI
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A53
Core NameCortex-A53
Process28 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1 V
VI/O1.8 V, 2.8 V, 3.3 V
OP Temperature-20 °C – 80 °C
Tjunction – 125 °C
Tstorage0 °C – 125 °C

Helio X10 T (MT6795T; T for turbo) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in early-2015. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 2.2 GHz and supports dual-channel LPDDR3-1866. This chip incorporates the PowerVR G6200 IGP operating at 700 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 4. This "turbo" variant of the X10 operates at 10% higher frequency.

This SoC is made of 2 clusters of 4-core each (Cortex-A53) linked together via a CCI-400, a NEON engine, and Cortex-R4 core for the second MCU subsystem.

Cache[edit]

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB2-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB4-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB16-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866
Supports ECCNo
Max Mem4 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth13.91 GiB/s
14,243.84 MiB/s
14.936 GB/s
14,935.749 MB/s
0.0136 TiB/s
0.0149 TB/s
Bandwidth
Single 6.95 GiB/s
Double 13.91 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0, 3.0
Ports8
UART
GP I/OYes


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR G6200
DesignerImagination Technologies
Max Displays2
Frequency700 MHz
0.7 GHz
700,000 KHz
OutputDSI
Max Resolution
DSI2560x1600
Standards
Direct3D10.0
OpenGL3.2
OpenCL1.2
OpenGL ES3.1
Vulkan1.0
  • OpenGL ES 3.0 3D graphic accelerator capable of processing 175M tri/sec and 2,800M pixel/sec @ 700 MHz
  • OpenVG 1.1 vector graphics accelerator

Wireless[edit]

Antu network-wireless-connected-100.svgWireless Communications
Cellular
2G
CSD Yes
GSM Yes
GPRS Yes
EDGE Yes
3G
UMTS
TD-SCDMAYes
DC-HSDPAYes
HSUPAYes
4G
LTE Advanced
E-UTRANYes
UE Cat4

Image[edit]

  • Integrated image signal processor supports 20 MP
  • Supports image stabilization
  • Supports video stabilization
  • Supports noise reduction
  • Supports lens shading correction
  • Supports AE/AWB/AF
  • Supports edge enhancement
  • Supports face detection and visual tracking
  • Hardware JPEG encoder

Video[edit]

  • HEVC decoder 4k2k @ 30fps
  • H.264 decoder (30fps/40Mbps)
  • Sorenson H.263/H.263 decoder (1080p @ 60fps/40Mbps)
  • MPEG-4 SP/ASP decoder (1080p @ 60fps/40Mbps)
  • DIVX4/DIVX5/DIVX6/DIVX HD/XVID decoder (1080p @ 60fps/40Mbps)
  • VP8 / VC-1 decoders
  • MPEG-4 / H.263 / H.264 / HEVC encoders

Audio[edit]

  • Audio content sampling rates 8kHz to 192kHz
  • Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
  • I2S, PCM
  • Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
  • Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
  • 7.1 channel MHL output

Utilizing devices[edit]

  • Meizu MX5
  • LeEco Le 1s
  • Xiaomi Redmi Note 2
  • HTC One X9
  • HTC One M9+
  • HTC One ME

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=mediatek/helio/mt6795t&oldid=81718"
Facts about "Helio X10 T (MT6795T) - MediaTek"
RDF feed
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus typeAMBA 4 AXI +
core count8 +
core nameCortex-A53 +
core voltage1 V (10 dV, 100 cV, 1,000 mV) +
designerMediaTek + and ARM Holdings +
familyHelio +
first announcedJuly 15, 2014 +
first launchedMarch 27, 2015 +
full page namemediatek/helio/mt6795t +
has 2g supporttrue +
has 3g supporttrue +
has 4g supporttrue +
has csd supporttrue +
has dc-hsdpa supporttrue +
has e-utran supporttrue +
has ecc memory supportfalse +
has edge supporttrue +
has gprs supporttrue +
has gsm supporttrue +
has hsupa supporttrue +
has lte advanced supporttrue +
has td-scdma supporttrue +
has umts supporttrue +
instance ofmicroprocessor +
integrated gpuPowerVR G6200 +
integrated gpu base frequency700 MHz (0.7 GHz, 700,000 KHz) +
integrated gpu designerImagination Technologies +
io voltage1.8 V (18 dV, 180 cV, 1,800 mV) +, 2.8 V (28 dV, 280 cV, 2,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description4-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description2-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateMarch 27, 2015 +
manufacturerTSMC +
market segmentMobile + and Embedded +
max cpu count1 +
max junction temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth13.91 GiB/s (14,243.84 MiB/s, 14.936 GB/s, 14,935.749 MB/s, 0.0136 TiB/s, 0.0149 TB/s) +
max memory channels2 +
max operating temperature80 °C +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureCortex-A53 +
min operating temperature-20 °C +
min storage temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberHelio X10 T +
nameMediaTek Helio X10 T +
part numberMT6795T + and MTK6795T +
process28 nm (0.028 μm, 2.8e-5 mm) +
seriesHelio X +
smp max ways1 +
supported memory typeLPDDR3-1866 +
technologyCMOS +
thread count8 +
used byMeizu MX5 +, LeEco Le 1s +, Xiaomi Redmi Note 2 +, HTC One X9 +, HTC One M9+ + and HTC One ME +
user equipment category4 +
word size64 bit (8 octets, 16 nibbles) +