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Difference between revisions of "amd/athlon mp/amp1900dms3c"
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{{amd title|Athlon MP 1900+}} | {{amd title|Athlon MP 1900+}} | ||
| − | {{ | + | {{chip |
| name = AMD Athlon MP 1900+ | | name = AMD Athlon MP 1900+ | ||
| no image = yes | | no image = yes | ||
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| max memory = 4 GiB | | max memory = 4 GiB | ||
| − | + | ||
| v core = 1.75 V | | v core = 1.75 V | ||
| v core tolerance = | | v core tolerance = | ||
| Line 61: | Line 61: | ||
| tstorage max = 100 °C | | tstorage max = 100 °C | ||
| − | + | |package module 1={{packages/amd/pga-453}} | |
| − | | package | ||
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| − | |||
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}} | }} | ||
The '''Athlon MP 1900+''' (OPN ''AMP1900DMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2001]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12 multiplier). This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany. | The '''Athlon MP 1900+''' (OPN ''AMP1900DMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2001]] for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12 multiplier). This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany. | ||
| Line 97: | Line 88: | ||
== Features == | == Features == | ||
{{x86 features | {{x86 features | ||
| − | |real= | + | |real=No |
| − | |protected= | + | |protected=No |
| − | |smm= | + | |smm=No |
| − | |fpu= | + | |fpu=No |
| − | |x8616= | + | |x8616=No |
| − | |x8632= | + | |x8632=No |
|x8664=No | |x8664=No | ||
|nx=No | |nx=No | ||
| − | + | |mmx=No | |
| − | + | |emmx=No | |
| − | |mmx= | ||
| − | |emmx= | ||
|sse=Yes | |sse=Yes | ||
|sse2=No | |sse2=No | ||
| Line 116: | Line 105: | ||
|sse42=No | |sse42=No | ||
|sse4a=No | |sse4a=No | ||
| + | |sse_gfni=No | ||
|avx=No | |avx=No | ||
| + | |avx_gfni=No | ||
|avx2=No | |avx2=No | ||
| − | | | + | |avx512f=No |
| + | |avx512cd=No | ||
| + | |avx512er=No | ||
| + | |avx512pf=No | ||
| + | |avx512bw=No | ||
| + | |avx512dq=No | ||
| + | |avx512vl=No | ||
| + | |avx512ifma=No | ||
| + | |avx512vbmi=No | ||
| + | |avx5124fmaps=No | ||
| + | |avx512vnni=No | ||
| + | |avx5124vnniw=No | ||
| + | |avx512vpopcntdq=No | ||
| + | |avx512gfni=No | ||
| + | |avx512vaes=No | ||
| + | |avx512vbmi2=No | ||
| + | |avx512bitalg=No | ||
| + | |avx512vpclmulqdq=No | ||
|abm=No | |abm=No | ||
|tbm=No | |tbm=No | ||
| Line 132: | Line 140: | ||
|clmul=No | |clmul=No | ||
|f16c=No | |f16c=No | ||
| + | |bfloat16=No | ||
|tbt1=No | |tbt1=No | ||
|tbt2=No | |tbt2=No | ||
|tbmt3=No | |tbmt3=No | ||
| + | |tvb=No | ||
|bpt=No | |bpt=No | ||
|eist=No | |eist=No | ||
| + | |sst=No | ||
|flex=No | |flex=No | ||
| + | |fastmem=No | ||
| + | |ivmd=No | ||
| + | |intelnodecontroller=No | ||
| + | |intelnode=No | ||
| + | |kpt=No | ||
| + | |tme=No | ||
| + | |mktme=No | ||
| + | |ptt=No | ||
| + | |intelrunsure=No | ||
| + | |mbe=No | ||
|isrt=No | |isrt=No | ||
| + | |sba=No | ||
|mwt=No | |mwt=No | ||
|sipp=No | |sipp=No | ||
| Line 154: | Line 176: | ||
|securekey=No | |securekey=No | ||
|osguard=No | |osguard=No | ||
| − | |smartmp= | + | |intqat=No |
| + | |dlboost=No | ||
| + | |3dnow=Yes | ||
| + | |e3dnow=Yes | ||
| + | |smartmp=No | ||
|powernow=No | |powernow=No | ||
| − | |amdv=No | + | |amdvi=No |
| + | |amdv=Yes | ||
| + | |amdsme=No | ||
| + | |amdtsme=No | ||
| + | |amdsev=No | ||
|rvi=No | |rvi=No | ||
| + | |smt=No | ||
| + | |sensemi=No | ||
| + | |xfr=No | ||
| + | |xfr2=No | ||
| + | |mxfr=No | ||
| + | |amdpb=No | ||
| + | |amdpb2=No | ||
| + | |amdpbod=No | ||
}} | }} | ||
* Advanced Configuration and Power Interface [[has feature::ACPI| ]] | * Advanced Configuration and Power Interface [[has feature::ACPI| ]] | ||
Latest revision as of 21:49, 3 September 2024
| Edit Values | |||||||||||
| AMD Athlon MP 1900+ | |||||||||||
| General Info | |||||||||||
| Designer | AMD | ||||||||||
| Manufacturer | AMD | ||||||||||
| Model Number | Athlon MP 1900+ | ||||||||||
| Part Number | AMP1900DMS3C | ||||||||||
| Market | Server | ||||||||||
| Introduction | December 12, 2001 (announced) December 12, 2001 (launched) | ||||||||||
| Release Price | $319 | ||||||||||
| Shop | Amazon | ||||||||||
| General Specs | |||||||||||
| Family | Athlon MP | ||||||||||
| Locked | Yes | ||||||||||
| Frequency | 1,600 MHz | ||||||||||
| Bus type | FSB | ||||||||||
| Bus speed | 133 MHz | ||||||||||
| Bus rate | 266 MT/s | ||||||||||
| Clock multiplier | 12 | ||||||||||
| CPUID | 662 | ||||||||||
| Microarchitecture | |||||||||||
| Microarchitecture | K7 | ||||||||||
| Platform | Athlon MP | ||||||||||
| Chipset | AMD-760MP | ||||||||||
| Core Name | Palomino | ||||||||||
| Core Family | 6 | ||||||||||
| Core Model | 6 | ||||||||||
| Core Stepping | 2 | ||||||||||
| Process | 180 nm | ||||||||||
| Transistors | 37,500,000 | ||||||||||
| Technology | CMOS | ||||||||||
| Die | 128 mm² | ||||||||||
| Word Size | 32 bit | ||||||||||
| Cores | 1 | ||||||||||
| Threads | 1 | ||||||||||
| Max Memory | 4 GiB | ||||||||||
| Multiprocessing | |||||||||||
| Max SMP | 2-Way (Multiprocessor) | ||||||||||
| Electrical | |||||||||||
| Vcore | 1.75 V | ||||||||||
| TDP | 66 W | ||||||||||
| TDP (Typical) | 58.9 W | ||||||||||
| Tjunction | 0 °C – 95 °C | ||||||||||
| Tcase | 0 °C – 95 °C | ||||||||||
| Tstorage | -40 °C – 100 °C | ||||||||||
| Packaging | |||||||||||
| |||||||||||
The Athlon MP 1900+ (OPN AMP1900DMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2001 for the server and workstation market. This MPU operated at 1.6 GHz with a FSB transfer rate of 266 MT/s (x12 multiplier). This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
Cache[edit]
- Main article: K7 § Cache
|
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics[edit]
This MPU has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
|
Supported x86 Extensions & Processor Features
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- Advanced Configuration and Power Interface
- Halt State
- Stop Grant State
Documents[edit]
Datasheets[edit]
- AMD Athlon MP Processor Model 6 OPGA Data Sheet for Multiprocessor Platforms; Publication # 25480 Rev: D; Issue Date: June 2002.
Others[edit]
- System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.
Facts about "Athlon MP 1900+ - AMD"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Athlon MP 1900+ - AMD#package + |
| base frequency | 1,600 MHz (1.6 GHz, 1,600,000 kHz) + |
| bus rate | 266 MT/s (0.266 GT/s, 266,000 kT/s) + |
| bus speed | 133 MHz (0.133 GHz, 133,000 kHz) + |
| bus type | FSB + |
| chipset | AMD-760MP + |
| clock multiplier | 12 + |
| core count | 1 + |
| core family | 6 + |
| core model | 6 + |
| core name | Palomino + |
| core stepping | 2 + |
| core voltage | 1.75 V (17.5 dV, 175 cV, 1,750 mV) + |
| cpuid | 662 + |
| designer | AMD + |
| die area | 128 mm² (0.198 in², 1.28 cm², 128,000,000 µm²) + |
| family | Athlon MP + |
| first announced | December 12, 2001 + |
| first launched | December 12, 2001 + |
| full page name | amd/athlon mp/amp1900dms3c + |
| has amd amd-v technology | true + |
| has feature | ACPI +, Halt State + and Stop Grant State + |
| has locked clock multiplier | true + |
| instance of | microprocessor + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
| ldate | December 12, 2001 + |
| manufacturer | AMD + |
| market segment | Server + |
| max case temperature | 368.15 K (95 °C, 203 °F, 662.67 °R) + |
| max cpu count | 2 + |
| max junction temperature | 368.15 K (95 °C, 203 °F, 662.67 °R) + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max storage temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
| microarchitecture | K7 + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
| model number | Athlon MP 1900+ + |
| name | AMD Athlon MP 1900+ + |
| package | OPGA-453 + |
| part number | AMP1900DMS3C + |
| platform | Athlon MP + |
| process | 180 nm (0.18 μm, 1.8e-4 mm) + |
| release price | $ 319.00 (€ 287.10, £ 258.39, ¥ 32,962.27) + |
| smp max ways | 2 + |
| tdp | 66 W (66,000 mW, 0.0885 hp, 0.066 kW) + |
| tdp (typical) | 58.9 W (58,900 mW, 0.079 hp, 0.0589 kW) + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 37,500,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |