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Difference between revisions of "intel/atom x3/x3-c3130"
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{{intel title|Atom x3-C3130}} | {{intel title|Atom x3-C3130}} | ||
| − | {{ | + | {{chip |
| name = Atom x3-C3130 | | name = Atom x3-C3130 | ||
| no image = Yes | | no image = Yes | ||
| image = | | image = | ||
| caption = | | caption = | ||
| − | | manufacturer = | + | | designer = Intel |
| + | | manufacturer = TSMC | ||
| model number = x3-C3130 | | model number = x3-C3130 | ||
| part number = | | part number = | ||
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| s-spec es = | | s-spec es = | ||
| − | | microarch = | + | | isa family = x86 |
| − | | platform = | + | | isa = x86-64 |
| − | | core name = | + | | microarch = Silvermont |
| + | | platform = SoFIA | ||
| + | | core name = SoFIA | ||
| core stepping = | | core stepping = | ||
| process = 28 nm | | process = 28 nm | ||
| Line 41: | Line 44: | ||
| max memory = 1024 MB | | max memory = 1024 MB | ||
| − | + | ||
| power = | | power = | ||
| sdp = | | sdp = | ||
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== Cache == | == Cache == | ||
{{cache info | {{cache info | ||
| − | + | |l2 cache=512 KiB | |
| − | + | |l2 break=1x512 KiB | |
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |l2 cache=512 | ||
| − | |l2 break=1x512 | ||
| − | |||
|l2 extra=(per 2 cores) | |l2 extra=(per 2 cores) | ||
| − | |l3 cache=0 | + | |l3 cache=0 KiB |
|l3 desc=No L3$ | |l3 desc=No L3$ | ||
}} | }} | ||
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== Features == | == Features == | ||
| − | {{ | + | {{x86 features |
| em64t = Yes | | em64t = Yes | ||
| nx = Yes | | nx = Yes | ||
Latest revision as of 15:15, 13 December 2017
| Edit Values | |
| Atom x3-C3130 | |
| General Info | |
| Designer | Intel |
| Manufacturer | TSMC |
| Model Number | x3-C3130 |
| Market | Mobile |
| Introduction | March 4, 2015 (announced) March 4, 2015 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Atom x3 |
| Series | C3000 |
| Locked | Yes |
| Frequency | 1000 MHz |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Silvermont |
| Platform | SoFIA |
| Core Name | SoFIA |
| Process | 28 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 2 |
| Threads | 2 |
| Max Memory | 1024 MB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| OP Temperature | -25 °C – 85 °C |
The x3-C3130 is a dual-core 64-bit system-on-chip designed by Intel and introduced in March 2015. The x3-C3130 is intel's first SoC to integrate a 3G modem. Manufactured in 28 nm process and operating at 1 GHz, this SoC is aimed at entry-level smart phones. This SoC integrates an Arm Mali-400 MP2 GPU.
Contents
Cache[edit]
| Cache Info [Edit Values] | ||
| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
1x512 KiB (per 2 cores) |
| L3$ | 0 KiB 0 MiB 0 B 0 GiB |
No L3$ |
Graphics[edit]
| Integrated Graphic Information | |
| GPU | Mali-400 MP2 |
| Displays | 1 |
| Frequency | 480 MHz 0.48 GHz
480,000 KHz |
| Output | DSI |
| OpenGL ES | 2.0 |
| Max DSI Res | 1280x800 @60 Hz |
Memory controller[edit]
| Integrated Memory Controller | |
| Type | LPDDR2-800 |
| Controllers | 1 |
| Channels | 1 |
| ECC Support | No |
| Max bandwidth | 3,200 MB/s |
| Max memory | 1024 MB |
Input/Output[edit]
- USB Revision: 2.0 OTG
- USB Ports: 1
- GP I/O: 2x I2C
- UART: 2x USIF
- GLONASS
Storage[edit]
- eMMC 4.41
Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Networking[edit]
- RF Transceiver: A-GOLD 620
- Baseband Functions: HSDPA+ 21Mbps HSUPA 5.8 Mbps, GSM/GPRS/EDGE, DSDS
- RF Transceiver Functions: Low power multimode multiband transceiver for 3G 2.5G 2G
- Wi-Fi: 802.11 B/G/N
- Bluetooth: 4.0 LE
- GPS & GLONASS
- FM Radio
- Protocol Stack: Intel Release 9 Protocol Stack
ISP/Camera[edit]
- Up to 13 MP/5 MP
Facts about "Atom x3-C3130 - Intel"