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A '''multiplexer''' ('''mux''') is a digital device that selects one of its inputs and connects it to its output. A set of inputs called select lines determine which input should be passed to the output. A multiplexer is unidirectional - the flow is only from input to output.
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{{title|Multiplexer (MUX)}}{{logic device
 +
|title            = Multiplexer
 +
|symbol title    = Typical Symbol (2:1 MUX)
 +
|symbol body      = [[File:Mux 2 1.svg|150px|center]]
 +
|functional body  = [[File:mux functional.gif|center]]
 +
|truth table      = {{truth table/mux}}
 +
}}
 +
A '''multiplexer''' ('''mux''') or a '''data selector''' or '''input selector''' is a [[combinational circuit]] device that selects one of ''N'' inputs and provides it on its output. A set of inputs called select lines determine which input should be passed to the output. For a 2:1 (two-to-one) MUX, when sel is 0, q = a and when sel is 1, q = b. A multiplexer with 2<sup>N</sup> input lines requires ''N'' select lines.
  
−
Multiplexers are useful in any application in which data must be chosen from multiple sources to a single destination. Multiplexers are also heavily used in I/O operations, data buses, and register files.
+
Multiplexers are useful in any application in which data must be chosen from multiple sources to a single destination. Multiplexers are also heavily used in I/O operations, data buses, and register files. Additionally multiplexers have also found their way to various other circuits such as adders.
  
−
A multiplexer with 2<sup>N</sup> input lines requires ''N'' select lines.
+
== Description ==
 +
<span style="float:right; display: inline-block;">[[File:3reg mux31.svg|200px|A simple selection of 3 [[register]]s.]]</span>
 +
A multiplxer is a device that receives multiple inputs from usually different sources. A set of select lines are then used to choose which of those inputs gets produced as output. Signals to the select lines usually come from a control unit that determines which, if any, of the signals should be routed to some destination. MUXes are core components in most digital systems as they can be used to pass the correct signal based on some conditional logic. For example, consider a [[data bus]] that is connected to [[register file|multiple]] memory [[register|storage units]]. One can use a multiplexer to select which of those lines should be going to the shared data bus.
  
−
A typical example of a multiplexer is shown on the right. When Sel is 0, Q = I<sub>1</sub>. When Sel is 1, Q = I<sub>2</sub>.
+
=== Enable/Tri-State ===
 +
It's often desirable to add an [[enable]] (or strobe) input ''EN'' to a multiplexer. An enable input makes the multiplexer operate. When ''EN = 0'', the output is [[High-Z]] or less commonly [[LOW]] (depending on the specific device). When ''EN = 1'', the multiplexer performs its operation depending on the selection line.
  
−
== Enable ==
+
'''Tri-state multiplexers''' are MUXes that do not force a [[LOW]] when enable is 0 but instead go into a [[High-Z]] state. Those types of multiplexers can be hooked up directly to a shared bus ensuring that only one signal is being generated on the bus at any given time.
−
It's often desirable to add an enable input ''EN'' to a multiplexer. An enable input makes the multiplexer operate. When ''EN = 0'', the output is  
 
−
0. When ''EN = 1'', the multiplexer performs its operation depending on the selection line.
 
  
−
== Variations ==
+
== Design ==
−
May different variations of multiplexers exit.
+
[[File:multiplxer general line count.svg|left|150px|2<sup>n</sup>:1 MUX]]
 +
For a multiplexer with <math>N</math> inputs, you also need <math>\lceil\log_2(N)\rceil</math> selection lines. It does mean that for multiplexers with odd number of inputs, some selection line combinations are not allowed (e.g. in a 3:1 MUX, the SEL=11 combination is not allowed). MUXes in the form <math>2^N</math>:1 can be expressed by
 +
:<math>\text{MUX}(I_0, ..., I_k) = \sum^{2^n-1}_{k=0}{m_k I_k}</math>
 +
Where <math>m_k</math> is the kth [[minterm]] of the variable.
  
−
=== 2:1 Mux ===
+
For 2, 4, and 8-input multiplexers the equations are thus:
−
A '''2:1 Mux''' is the simplest multiplexer that can be made. Its selection lines is made of a single bit. A truth table is provided on the right. The logic function of a 2:1 Mux is: Q=(A ∧ <span style="text-decoration:overline;">S</span>) ∨ ( B ∧ S)
 
  
−
Very fast, CMOS-based, 2:1 Mux devices can be built using two [[transmission gate]]s as shown below. Note that the implementation below is a nonrestoring multiplexer.
+
:<math>
 +
\begin{align}
 +
\text{MUX21}(a, b)                &= (A\overline{S_0})+(BS_0) \\
 +
\text{MUX41}(a, b, c, d)          &= (A\overline{S_0 S_1})+(B\overline{S_0}S_1)+(C S_0\overline{S_1})+(D S_0 S_1) \\
 +
\text{MUX81}(a, b, c, d, e, f, g) &= (A\overline{S_0 S_1 S_2})+(B\overline{S_0 S_1}S_2)+(C \overline{S_0} S_1 \overline{S_2})+(D \overline{S_0} S_1 S_2)+(E S_0 \overline{S_1 S_2})+(F S_0 S_1 \overline{S_2})+(G S_0 S_1 S_2)
 +
\end{align}
 +
</math>
 +
{{clear}}
 +
 
 +
== Implementations ==
 +
Many different variations of multiplexers exist. Typically larger multiplxers (over 8 or 16 inputs) are built using smaller multiplxers using a [[/tree|multiplexer tree]].
 +
 
 +
=== 2:1 MUX (MUX21) ===
 +
{| class="wikitable" style="float: right;"
 +
! colspan="4" | 2:1 Mux
 +
|-
 +
! Sel !! A !! B !! Q
 +
|-
 +
| 0 || 0 || {{X}} || 0
 +
|-
 +
| 0 || 1 || {{X}} || 1
 +
|-
 +
| 1 || {{X}} || 0 || 0
 +
|-
 +
| 1 || {{X}} || 1 || 1
 +
|}
 +
[[File:Mux_2_1_equivalence.svg|left|200px]]
 +
[[File:mux21 k-map.svg|left|200px|thumb|A [[K-Map]] of a 2:1 Multiplexer.]]
 +
The simplest multiplexer is the '''2:1 MUX''' (or '''MUX21''') which simply selects its output from just two possible inputs. Its selection lines is therefore made of a [[bit|single bit]]. A [[truth table]] is provided on the right.
 +
 
 +
 
 +
The [[K-Map]] for that truth table is provided on the left. From there the [[sum of minterms]] and the [[logic function]] for a 2:1 MUX can be derived.
 +
 
 +
 
 +
:<math>\sum m(3,4,6,7) = (A \land \overline{S}) \lor (B \land S)</math>
 +
{{clear}}
 +
 
 +
====CMOS====
 +
A very fast and compact, [[CMOS]]-based [[pass-transistor logic|PTL logic]], 2:1 MUX device can be built using two [[transmission gate]]s as shown below. The top transmission gate controls if the input from ''A'' should pass to the output while the bottom transmission gate does the same for the ''B'' input. A single [[inverter]] is used to invert the selection line value to one of the gates so that only one of them (e.i. input A or input B) is allowed to pass. While smaller overall, this multiplexer is also [[nonrestoring]].
 +
 
 +
{|
 +
| [[File:MUX21 using transmission gates.svg|200px]] || style="padding-left: 50px;" | [[File:MUX21 using cmos tranmission.svg|200px]]
 +
|}
 +
 
 +
{{expand section}}
 +
A 2:1 MUX can also be built using an [[AOI222]] gate.
 +
{{clear}}
 +
 
 +
=== 3:1 MUX ===
 +
{{empty section}}
  
 
=== 4:1 Mux ===
 
=== 4:1 Mux ===
 +
{| class="wikitable" style="float: right;"
 +
|+ 4:1 Mux
 +
|-
 +
! Sel<1> !! Sel<0> !! I<0> !! I<1> !! I<2> !! I<3> !! Q
 +
|-
 +
| 0 || 0 || 0 || X || X || X || 0
 +
|-
 +
| 0 || 0 || 1 || X || X || X || 1
 +
|-
 +
| 0 || 1 || X || 0 || X || X || 0
 +
|-
 +
| 0 || 1 || X || 1 || X || X || 1
 +
|-
 +
| 1 || 0 || X || X || 0 || X || 0
 +
|-
 +
| 1 || 0 || X || X || 1 || X || 1
 +
|-
 +
| 1 || 1 || X || X || X || 0 || 0
 +
|-
 +
| 1 || 1 || X || X || X || 1 || 1
 +
|}
 
A '''4:1''' Multiplexer is a common multiplexer that takes selects one input among 4 and connects it to its output based on a 2-bit select line. There are many way to construct a 4:1 Mux, one possibility is using 2:1 Mux as shown below:
 
A '''4:1''' Multiplexer is a common multiplexer that takes selects one input among 4 and connects it to its output based on a 2-bit select line. There are many way to construct a 4:1 Mux, one possibility is using 2:1 Mux as shown below:
  
−
Alternatively, a 4:1 Mux can be built out of basic gates. Its function is Q = <math>(A \land \overline S_0 \land \overline S_1) \lor (B \land \overline S_0 \land S_1) \lor (C \land S_0 \land \overline S_1) \lor (D  \land S_0 \land S_1)</math>
+
[[File:Mux 4 1 using mux 2 1.svg|200px|center]]
 +
 
 +
Alternatively, a 4:1 Mux can be built out of basic gates. Its function is shown below:
 +
 
 +
Q = <math>(A \land \overline S_0 \land \overline S_1) \lor (B \land S_0 \land\overline S_1) \lor (C \land\overline S_0 \land S_1) \lor (D  \land S_0 \land S_1)</math>
  
 
Where A, B, C, and D are the four inputs. Q is the output.
 
Where A, B, C, and D are the four inputs. Q is the output.
  
−
=== Larger Multiplexers ===
+
====CMOS====
−
Multiplexers generally only come in a few common sizes. Even in ASIC design, arbitrary sized multiplexers are not always offered. Large multiplexers can always be built from a collection of smaller ones. Consider a register file with 32 registers where we only want to select a single register at any given time. Such multiplexer can be design from four 8:1 Mux.
+
{{empty section}}
 +
 
 +
=== 8:1 MUX ===
 +
{{empty section}}
 +
 
 +
=== Large Multiplexers ===
 +
{{main|/tree|l1=Multiplexer Tree}}
 +
Multiplexers generally only come in a few common sizes. Even in [[ASIC]] design, arbitrary sized multiplexers are not always offered. Large multiplexers can always be built from a collection of smaller ones. Consider a [[register file]] with 32 registers where we only want to select a single register at any given time. Such multiplexer can be design from four 8:1 Mux.
 +
 
 +
== Discrete Chips ==
 +
Various multiplexers are available in discrete chips as well for both [[7400 series]] and [[4000 series]].
 +
 
 +
=== [[7400 series]] chips ===
 +
{| class="wikitable sortable"
 +
! Device Number !! Name !! Description
 +
|-
 +
| {{74s|74150}}  || 16:1 MUX    || Output is inverted input
 +
|-
 +
| {{74s|74151}}  || 8:1 MUX      || Output is inverted input
 +
|-
 +
| {{74s|74151A}} || 8:1 MUX      || Output is inverted input
 +
|-
 +
| {{74s|74152}}  || 8:1 MUX      || Complementary outputs
 +
|-
 +
| {{74s|74153}}  || Dual 4:1 MUX || Output same as input
 +
|-
 +
| {{74s|74157}}  || Quad 2:1 MUX || Output same as input
 +
|-
 +
| {{74s|74158}}  || Quad 2:1 MUX || Output is inverted input
 +
|-
 +
| {{74s|74257}}  || Quad 2:1 MUX || Output same as input, High-Z Enable
 +
|-
 +
| {{74s|74298}}  || Quad 2:1 MUX with Register || MUX with an [[SR latch]]
 +
|-
 +
| {{74s|74399}}  || Quad 2:1 MUX with Register || MUX with an [[SR latch]]
 +
|-
 +
| {{74s|74398}}  || Quad 2:1 MUX with Register || MUX with an [[SR latch]] / Complementary outputs
 +
|-
 +
|}
 +
 
 +
=== [[4000 series]] chips ===
 +
{| class="wikitable sortable"
 +
! Device Number !! Name !! Description
 +
|-
 +
| {{40s|4512}}  || 8:1 MUX with EN    || Output same as input, [[High-Z]] Enable
 +
|-
 +
| {{40s|4514}}  || 16:1 MUX with EN/Register || Output same as input
 +
|-
 +
| {{40s|4515}}  || 16:1 MUX with EN/Register || Output is inverted input
 +
|-
 +
| {{40s|4539}}  || Dual 4:1 MUX              || Output same as input
 +
|-
 +
| {{40s|40257}} || Quad 2:1 MUX with EN      || Complementary outputs, [[High-Z]] Enable
 +
|}
  
 
==== 74151 - 8:1 Mux ====
 
==== 74151 - 8:1 Mux ====
−
A common multiplexer is the 8:1 Mux which selects one of 8 bits of input. The 74151 is a popular 16-pin DIP IC that implements an 8:1 mux. Note that the implementation below is an active-low.
+
[[File:Mux 8 1 equivalence.svg|500px|right|thumb|74151 IC Chip]]
 +
A common multiplexer is the 8:1 Mux which selects one of 8 bits of input. The [[74151]] is a popular 16-pin [[DIP]] IC that implements an 8:1 mux. Note that the implementation below is an active-low.
 +
 
 +
To the right is the typical schematic of the 74151, 16-pin DIP IC. Vcc is on pin 16 and GND is on pin 8. Pins 5 and 6 are the outputs, the output on pin 6 is the inverted version of the output on pin 5. The enable is on pin 7.
 +
 
 +
{| class="wikitable"
 +
|-
 +
! colspan="6" | 8:1 Mux
 +
|-
 +
! colspan="4" | Inputs !! rowspan="2" colspan="2" | Output
 +
|-
 +
! colspan="3" | Select !! Enable
 +
|-
 +
! Sel<0> !! Sel<1> !! Sel<2> !! EN !! Q !! <span style="text-decoration:overline;">Q</span>
 +
|-
 +
| X || X || X || 1 || 1 || 0
 +
|-
 +
|0 || 0 || 0 || 0 || I<0> || <span style="text-decoration:overline;">I<0></span>
 +
|-
 +
|0 || 0 || 1 || 0 || I<1> || <span style="text-decoration:overline;">I<1></span>
 +
|-
 +
|0 || 1 || 0 || 0 || I<2> || <span style="text-decoration:overline;">I<2></span>
 +
|-
 +
|0 || 1 || 1 || 0 || I<3> || <span style="text-decoration:overline;">I<3></span>
 +
|-
 +
|1 || 0 || 0 || 0 || I<4> || <span style="text-decoration:overline;">I<4></span>
 +
|-
 +
|1 || 0 || 1 || 0 || I<5> || <span style="text-decoration:overline;">I<5></span>
 +
|-
 +
|1 || 1 || 0 || 0 || I<6> || <span style="text-decoration:overline;">I<6></span>
 +
|-
 +
|1 || 1 || 1 || 0 || I<7> || <span style="text-decoration:overline;">I<7></span>
 +
|}
  
−
Above was the typical schematic of the 74151, 16-pin DIP IC. Vcc is on pin 16 and GND is on pin 8. Pins 5 and 6 are the outputs, the output on pin 6 is the inverted version of the output on pin 5. The enable is on pin 7.
+
[[File:74151.svg|left|thumb|300px|74151 IC 8:1 MUX]]
 +
{{clear}}
  
−
== Tri-State Outputs ==
+
== See also ==
−
Some commercial multiplexers have tri-state outputs. When the EN input is LOW, instead of the output being forced into 0, it gets forced into a Hi-Z state.
+
* [[choose function]]
 +
* [[adders]]
 +
** [[multiplexer adder]]
 +
** [[carry-select adder]]
  
 
[[Category:Logic gates]]
 
[[Category:Logic gates]]

Latest revision as of 10:53, 18 November 2018

Multiplexer
Typical Symbol (2:1 MUX)
mux21.svg
Functional
mux functional.gif
Truth Table
2:1 MUX
Inputs Outputs
Sel A B Q
0 0 X 0
0 1 X 1
1 X 0 0
1 X 1 1
Other Gates
Buffer TriBuffer NOT
AND OR XOR
NAND NOR XNOR
Trans AOI OAI
MAJ INH IMPLY
NIMPLY
Other Components
Plexers
MUX DEMUX Encoder
Decoder Pri-Encoder
ALU
Adder Subtractor Multiplier
Divider Shifter Rotator
MAC Comparator Negator
Memory
D latch D flip-flop SR latch
JK flip-flop T flip-flop Register
Register file SRAM Counter
ROM CAM DRAM
I/O
Shift register SIPO PISO
ADC DAC

A multiplexer (mux) or a data selector or input selector is a combinational circuit device that selects one of N inputs and provides it on its output. A set of inputs called select lines determine which input should be passed to the output. For a 2:1 (two-to-one) MUX, when sel is 0, q = a and when sel is 1, q = b. A multiplexer with 2N input lines requires N select lines.

Multiplexers are useful in any application in which data must be chosen from multiple sources to a single destination. Multiplexers are also heavily used in I/O operations, data buses, and register files. Additionally multiplexers have also found their way to various other circuits such as adders.

Description[edit]

A simple selection of 3 registers. A multiplxer is a device that receives multiple inputs from usually different sources. A set of select lines are then used to choose which of those inputs gets produced as output. Signals to the select lines usually come from a control unit that determines which, if any, of the signals should be routed to some destination. MUXes are core components in most digital systems as they can be used to pass the correct signal based on some conditional logic. For example, consider a data bus that is connected to multiple memory storage units. One can use a multiplexer to select which of those lines should be going to the shared data bus.

Enable/Tri-State[edit]

It's often desirable to add an enable (or strobe) input EN to a multiplexer. An enable input makes the multiplexer operate. When EN = 0, the output is High-Z or less commonly LOW (depending on the specific device). When EN = 1, the multiplexer performs its operation depending on the selection line.

Tri-state multiplexers are MUXes that do not force a LOW when enable is 0 but instead go into a High-Z state. Those types of multiplexers can be hooked up directly to a shared bus ensuring that only one signal is being generated on the bus at any given time.

Design[edit]

2n:1 MUX

For a multiplexer with Equation upper N inputs, you also need Equation left ceiling log Subscript 2 Baseline left-parenthesis upper N right-parenthesis right ceiling selection lines. It does mean that for multiplexers with odd number of inputs, some selection line combinations are not allowed (e.g. in a 3:1 MUX, the SEL=11 combination is not allowed). MUXes in the form Equation 2 Superscript upper N :1 can be expressed by

Equation MUX left-parenthesis upper I 0 comma period period period comma upper I Subscript k Baseline right-parenthesis equals sigma-summation Underscript k equals 0 Overscript 2 Superscript n Baseline minus 1 Endscripts m Subscript k Baseline upper I Subscript k Baseline

Where Equation m Subscript k is the kth minterm of the variable.

For 2, 4, and 8-input multiplexers the equations are thus:

Equation StartLayout 1st Row 1st Column MUX 21 left-parenthesis a comma b right-parenthesis 2nd Column equals left-parenthesis upper A upper S 0 overbar right-parenthesis plus left-parenthesis upper B upper S 0 right-parenthesis 2nd Row 1st Column MUX 41 left-parenthesis a comma b comma c comma d right-parenthesis 2nd Column equals left-parenthesis upper A ModifyingAbove upper S 0 upper S 1 With bar right-parenthesis plus left-parenthesis upper B upper S 0 overbar upper S 1 right-parenthesis plus left-parenthesis upper C upper S 0 upper S 1 overbar right-parenthesis plus left-parenthesis upper D upper S 0 upper S 1 right-parenthesis 3rd Row 1st Column MUX 81 left-parenthesis a comma b comma c comma d comma e comma f comma g right-parenthesis 2nd Column equals left-parenthesis upper A ModifyingAbove upper S 0 upper S 1 upper S 2 With bar right-parenthesis plus left-parenthesis upper B ModifyingAbove upper S 0 upper S 1 With bar upper S 2 right-parenthesis plus left-parenthesis upper C upper S 0 overbar upper S 1 upper S 2 overbar right-parenthesis plus left-parenthesis upper D upper S 0 overbar upper S 1 upper S 2 right-parenthesis plus left-parenthesis upper E upper S 0 ModifyingAbove upper S 1 upper S 2 With bar right-parenthesis plus left-parenthesis upper F upper S 0 upper S 1 upper S 2 overbar right-parenthesis plus left-parenthesis upper G upper S 0 upper S 1 upper S 2 right-parenthesis EndLayout

Implementations[edit]

Many different variations of multiplexers exist. Typically larger multiplxers (over 8 or 16 inputs) are built using smaller multiplxers using a multiplexer tree.

2:1 MUX (MUX21)[edit]

2:1 Mux
Sel A B Q
0 0 X 0
0 1 X 1
1 X 0 0
1 X 1 1
Mux 2 1 equivalence.svg
A K-Map of a 2:1 Multiplexer.

The simplest multiplexer is the 2:1 MUX (or MUX21) which simply selects its output from just two possible inputs. Its selection lines is therefore made of a single bit. A truth table is provided on the right.


The K-Map for that truth table is provided on the left. From there the sum of minterms and the logic function for a 2:1 MUX can be derived.


Equation sigma-summation m left-parenthesis 3 comma 4 comma 6 comma 7 right-parenthesis equals left-parenthesis upper A logical-and upper S overbar right-parenthesis logical-or left-parenthesis upper B logical-and upper S right-parenthesis

CMOS[edit]

A very fast and compact, CMOS-based PTL logic, 2:1 MUX device can be built using two transmission gates as shown below. The top transmission gate controls if the input from A should pass to the output while the bottom transmission gate does the same for the B input. A single inverter is used to invert the selection line value to one of the gates so that only one of them (e.i. input A or input B) is allowed to pass. While smaller overall, this multiplexer is also nonrestoring.

MUX21 using transmission gates.svg MUX21 using cmos tranmission.svg
New text document.svg This section requires expansion; you can help adding the missing info.

A 2:1 MUX can also be built using an AOI222 gate.

3:1 MUX[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

4:1 Mux[edit]

4:1 Mux
Sel<1> Sel<0> I<0> I<1> I<2> I<3> Q
0 0 0 X X X 0
0 0 1 X X X 1
0 1 X 0 X X 0
0 1 X 1 X X 1
1 0 X X 0 X 0
1 0 X X 1 X 1
1 1 X X X 0 0
1 1 X X X 1 1

A 4:1 Multiplexer is a common multiplexer that takes selects one input among 4 and connects it to its output based on a 2-bit select line. There are many way to construct a 4:1 Mux, one possibility is using 2:1 Mux as shown below:

Mux 4 1 using mux 2 1.svg

Alternatively, a 4:1 Mux can be built out of basic gates. Its function is shown below:

Q = Equation left-parenthesis upper A logical-and upper S overbar Subscript 0 Baseline logical-and upper S overbar Subscript 1 Baseline right-parenthesis logical-or left-parenthesis upper B logical-and upper S 0 logical-and upper S overbar Subscript 1 Baseline right-parenthesis logical-or left-parenthesis upper C logical-and upper S overbar Subscript 0 Baseline logical-and upper S 1 right-parenthesis logical-or left-parenthesis upper D logical-and upper S 0 logical-and upper S 1 right-parenthesis

Where A, B, C, and D are the four inputs. Q is the output.

CMOS[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

8:1 MUX[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Large Multiplexers[edit]

Main article: Multiplexer Tree

Multiplexers generally only come in a few common sizes. Even in ASIC design, arbitrary sized multiplexers are not always offered. Large multiplexers can always be built from a collection of smaller ones. Consider a register file with 32 registers where we only want to select a single register at any given time. Such multiplexer can be design from four 8:1 Mux.

Discrete Chips[edit]

Various multiplexers are available in discrete chips as well for both 7400 series and 4000 series.

7400 series chips[edit]

Device Number Name Description
74150 16:1 MUX Output is inverted input
74151 8:1 MUX Output is inverted input
74151A 8:1 MUX Output is inverted input
74152 8:1 MUX Complementary outputs
74153 Dual 4:1 MUX Output same as input
74157 Quad 2:1 MUX Output same as input
74158 Quad 2:1 MUX Output is inverted input
74257 Quad 2:1 MUX Output same as input, High-Z Enable
74298 Quad 2:1 MUX with Register MUX with an SR latch
74399 Quad 2:1 MUX with Register MUX with an SR latch
74398 Quad 2:1 MUX with Register MUX with an SR latch / Complementary outputs

4000 series chips[edit]

Device Number Name Description
4512 8:1 MUX with EN Output same as input, High-Z Enable
4514 16:1 MUX with EN/Register Output same as input
4515 16:1 MUX with EN/Register Output is inverted input
4539 Dual 4:1 MUX Output same as input
40257 Quad 2:1 MUX with EN Complementary outputs, High-Z Enable

74151 - 8:1 Mux[edit]

74151 IC Chip

A common multiplexer is the 8:1 Mux which selects one of 8 bits of input. The 74151 is a popular 16-pin DIP IC that implements an 8:1 mux. Note that the implementation below is an active-low.

To the right is the typical schematic of the 74151, 16-pin DIP IC. Vcc is on pin 16 and GND is on pin 8. Pins 5 and 6 are the outputs, the output on pin 6 is the inverted version of the output on pin 5. The enable is on pin 7.

8:1 Mux
Inputs Output
Select Enable
Sel<0> Sel<1> Sel<2> EN Q Q
X X X 1 1 0
0 0 0 0 I<0> I<0>
0 0 1 0 I<1> I<1>
0 1 0 0 I<2> I<2>
0 1 1 0 I<3> I<3>
1 0 0 0 I<4> I<4>
1 0 1 0 I<5> I<5>
1 1 0 0 I<6> I<6>
1 1 1 0 I<7> I<7>
74151 IC 8:1 MUX

See also[edit]

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