An **adder** (sometimes called a **summer**) is a device that adds two numbers and generates the summed result.

In digital circuits, an adder usually adds two *N*-bit numbers and generates an *N*-bit number. In addition to generating a sum, adders often also generate an overflow flag and a carry flag. Adders are used in many parts of the microprocessor such as the ALU, PC, counters, calculating effective addresses and table indices, multipliers, filters, and in various other components.

In analog circuits, adders usually deal with two real numbers instead.

## Contents

- 1 Basic design
- 2 BCD Adders
- 3 Advanced Designs
- 4 See also

## Basic design[edit]

A 1-bit adder adds two single-bit values together. There are four such possible operations. All but the 1+1 operation result in a single-digit sum. The 1+1 operation produces a sum with two digits. The higher significant bit of that value is known as a carry. The digital component that performs the addition of two bits is called a **half adder**. When two multi-bit numbers are added together, the carry out from the lower bit must be accounted for in the higher addition of the higher bits. When a half adder accounts for a carry in, it becomes a **full adder**.

### Half Adders (HA)[edit]

*Main article: Half adder*

Half Adder | ||||
---|---|---|---|---|

Input | C_{out} |
S | Q_{10}
| |

0 | 0 | 0 | 0 | 0 |

0 | 1 | 0 | 1 | 1 |

1 | 0 | 0 | 1 | 1 |

1 | 1 | 1 | 0 | 2 |

A **half adder** is a simple device that adds two single bit inputs. The result of a half adder (in base 10) is either 0, 1, or 2. Two bits are required to represent that output; they are called the **sum** S and **carry-out** C_{out}. The carry-out of one half adder is typically used as the carry-in of the next half adder. For that reason it is said to have double the weight of the other bit.

The sum is 1 only when one of the operands is 1, otherwise it's 0. This can be realized by simply XORing them together. The carry out bit is one only when both addends are one; ANDing the two bits will generate the desired output.

### Full Adder (FA)[edit]

*Main article: full adder*

A major drawback of a half adder is that it lacks the ability to add two bits and account for a carry-in that might have been brought from the previous digit. As previously stated, the carry-out of one half adder is the carry-in of the next half adder. A **full adder** is a simple device that can receive a carry-in bit input in addition to adding two single bit inputs. A full adder has three inputs A, B, and C_{in} and two outputs S and C_{out}. Full adders are typically combined together in a cascading way (C_{in} to _{out}), creating *N*-bit adders (16, 32, 64, etc..).

The sum output can be expressed as:

## BCD Adders[edit]

*Main article: BCD Adder*

Most adders typically use the binary numeral system, however they can use any other numerical representation such as binary-coded decimal. Binary adders are typically simpler to design when compared to a BCD adder where roughly 20 percent more circuitry is required.

## Advanced Designs[edit]

Due to the adder's central role in so many digital circuits, it has been the subject of many researches. Various different designs have been developed over the years to meet a broad range of requirements (e.g. complexity, cost, space, and time trade-offs).

### PGK Cell[edit]

This section is empty; you can help add the missing info by editing this page. |

Many complex adder designs relay on the ability to calculate carry bits quickly.

### Two-operand adders[edit]

#### Ripple-carry adder (RCA)[edit]

*Main article: Ripple-carry adder*

This section is empty; you can help add the missing info by editing this page. |

#### Carry-lookahead adder (CLA)[edit]

*Main article: Carry-lookahead adder*

This section is empty; you can help add the missing info by editing this page. |

##### Lookahead carry unit (LCU)[edit]

*Main article: Lookahead carry unit*

This section is empty; you can help add the missing info by editing this page. |

##### Ripple-block carry-lookahead adder (RCLA)[edit]

*Main article: Ripple-block carry-lookahead adder*

This section is empty; you can help add the missing info by editing this page. |

##### Block carry-lookahead adder (BCLA)[edit]

*Main article: Block carry-lookahead adder*

This section is empty; you can help add the missing info by editing this page. |

#### Ling adder[edit]

*Main article: Ling adder*

This section is empty; you can help add the missing info by editing this page. |

#### Manchester carry-chain adder[edit]

*Main article: Manchester carry-chain adder*

This section is empty; you can help add the missing info by editing this page. |

#### Carry-select adder[edit]

*Main article: Carry-select adder*

This section is empty; you can help add the missing info by editing this page. |

#### Carry-skip adder[edit]

*Main article: Carry-skip adder*

This section is empty; you can help add the missing info by editing this page. |

#### Conditional-Sum Adder[edit]

*Main article: Conditional-sum adder*

This section is empty; you can help add the missing info by editing this page. |

#### Parallel-prefix adders[edit]

*Main article: Parallel-prefix adder*

Parallel prefix adders are a class of highly-efficient binary adders. Several parallel-prefix adder topologies have been developed that exhibit various space and time characteristics.

##### Beaumont-Smith adder (BSA)[edit]

*Main article: Beaumont-Smith adder*

This section is empty; you can help add the missing info by editing this page. |

##### Ladner-Fischer adder[edit]

*Main article: Ladner-Fischer adder*

This section is empty; you can help add the missing info by editing this page. |

##### Kogge-Stone adder[edit]

*Main article: Kogge-Stone adder*

This section is empty; you can help add the missing info by editing this page. |

##### Brent-Kung adder[edit]

*Main article: Brent-Kung adder*

{{Brent-Kung adder is a very well-known logarithmic adder architecture that gives an optimal number of stages from input to all outputs but with asymmetric loading on all intermediate stages. It is one of the parallel prefix adders. Parallel prefix adders are unique class of adders that are based on the use of generate and propagate signals. The cost and wiring complexity is less in brent kung adders. But the gate level depth of Brent-Kung adders is 0 (log2(n)), so the speed is lower.}}

##### Han-Carlson adder[edit]

*Main article: Han-Carlson adder*

This section is empty; you can help add the missing info by editing this page. |

### Multi-operand adders[edit]

(Partial product accumulator)

#### Carry-save adder array[edit]

*Main article: Carry-save adder array*

This section is empty; you can help add the missing info by editing this page. |

#### Wallace tree adder[edit]

*Main article: Wallace tree adder*

This section is empty; you can help add the missing info by editing this page. |

#### Balanced delay tree adder[edit]

*Main article: Balanced delay tree adder*

This section is empty; you can help add the missing info by editing this page. |

#### Overturned-stairs tree adder[edit]

*Main article: Overturned-stairs tree adder*

This section is empty; you can help add the missing info by editing this page. |

#### Compressors trees[edit]

This section is empty; you can help add the missing info by editing this page. |

##### 3:2 compressor tree[edit]

*Main article: 3:2 compressor tree*

This section is empty; you can help add the missing info by editing this page. |

##### 4:2 compressor tree[edit]

*Main article: 4:2 compressor tree*

This section is empty; you can help add the missing info by editing this page. |

##### Dadda tree[edit]

*Main article: Dadda tree*

This section is empty; you can help add the missing info by editing this page. |