From WikiChip
Difference between revisions of "hisilicon/kirin/810"
< hisilicon‎ | kirin

(→‎Utilizing devices)
 
(13 intermediate revisions by 11 users not shown)
Line 31: Line 31:
 
[[File:k810.jpg|right|thumb]]
 
[[File:k810.jpg|right|thumb]]
 
'''Kirin 810''' is a {{arch|64}} [[octa-core]] mid-range performance mobile [[ARM]] SoC introduced by [[HiSilicon]] in mid-[[2019]]. This chip, which is fabricated on [[TSMC]]'s [[7 nm process]], features two {{armh|Cortex-A76|l=arch}} [[big cores]] operating at up to 2.27 GHz along with six {{armh|Cortex-A55}} [[little cores]] operating at up to 1.88 GHz. The 810 incorporates [[ARM Holdings|ARM]]'s {{armh|Mali-G52}} MP6 GPU.
 
'''Kirin 810''' is a {{arch|64}} [[octa-core]] mid-range performance mobile [[ARM]] SoC introduced by [[HiSilicon]] in mid-[[2019]]. This chip, which is fabricated on [[TSMC]]'s [[7 nm process]], features two {{armh|Cortex-A76|l=arch}} [[big cores]] operating at up to 2.27 GHz along with six {{armh|Cortex-A55}} [[little cores]] operating at up to 1.88 GHz. The 810 incorporates [[ARM Holdings|ARM]]'s {{armh|Mali-G52}} MP6 GPU.
 +
 +
== Cache ==
 +
{{main|arm holdings/microarchitectures/cortex-a55#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a76#Memory_Hierarchy|l1=Cortex-A55 § Cache|l2=Cortex-A76 § Cache}}
 +
 +
For the {{armh|Cortex-A76|l=arch}}:
 +
 +
{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=2x64 KiB
 +
|l1d cache=128 KiB
 +
|l1d break=2x64 KiB
 +
|l2 cache=1 MiB
 +
|l2 break=2x512 KiB
 +
}}
 +
 +
For the {{armh|Cortex-A55|l=arch}}:
 +
 +
{{cache size
 +
|l1 cache=384 KiB
 +
|l1i cache=192 KiB
 +
|l1i break=6x32 KiB
 +
|l1d cache=192 KiB
 +
|l1d break=6x32 KiB
 +
|l2 cache=768 KiB
 +
|l2 break=6x128 KiB
 +
}}
 +
  
 
== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=LPDDR4
+
|type=LPDDR4X-4266
−
|type 2=LPDDR3
 
 
|ecc=No
 
|ecc=No
−
|max mem=6 GiB - 10 GIB
+
|max mem=8 GiB
 
|controllers=1
 
|controllers=1
−
|channels=2
+
|channels=4
−
|width=32 bit
+
|width=16 bit
 +
|max bandwidth=31.78 GiB/s
 +
|bandwidth dchan=15.89 GiB/s
 +
|bandwidth qchan=31.78 GiB/s
 
}}
 
}}
 +
  
 
== Graphics ==
 
== Graphics ==
Line 50: Line 81:
 
| max displays        = 2
 
| max displays        = 2
 
| max memory          =  
 
| max memory          =  
−
| frequency          =  
+
| frequency          = 850 MHz
 
| max frequency      =  
 
| max frequency      =  
 +
 +
 +
| directx ver        = 12
 +
| opengl es ver      = 3.2
 +
| openvg ver        = 1.1
 +
| opencl ver        = 2.0
 +
| vulkan ver        = 1.0
  
 
|max res generic      = 2340x1080
 
|max res generic      = 2340x1080
Line 59: Line 97:
 
** Decode: 1080p @ 60fps
 
** Decode: 1080p @ 60fps
 
** Encode: 1080p @ 30fps
 
** Encode: 1080p @ 30fps
 +
 +
== NPU ==
 +
This is the first [[neural processing unit]] to use their own homegrown NPU based on Hisilicon's first generation {{hisilicon|Da Vinci}} architecture. The NPU contains one processor core and a scheduling core.
  
 
== ISP ==
 
== ISP ==
−
* 40 MP+ 24 MP
+
* 40 MP+ 24 MP dual
 +
48 single
  
−
== Connectivity ==
+
== Wireless ==
−
* WiFi
 
−
** 802.11 a/b/g/n, 2.4GHz
 
−
* Bluetooth 4.2
 
 
* LTE Modem
 
* LTE Modem
−
** Downlink
+
** DL: Up to [[User Equipment]] (UE) category 12
−
*** Cat-12, 600 Mbps
+
*** Downlink of up to 600 Mbps
−
** Uplink
+
** UL: Up to [[User Equipment]] (UE) category 13
−
*** Cat-13, 150 Mbps
+
*** Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
 +
* Wi-Fi 802.11 ac
 +
* Bluetooth 5
 +
* NFC
 +
* GPS / A-GPS / GLONASS / BDS
  
 
== Location ==
 
== Location ==
Line 78: Line 121:
 
== Utilizing devices ==
 
== Utilizing devices ==
 
* [[used by::Huawei Nova 5]]
 
* [[used by::Huawei Nova 5]]
−
 
+
* [[used by::Huawei Honor 9x]]
−
{{expand list}}
+
* [[used by::Huawei Honor 9x Pro]]
 +
* [[used by::Huawei Mate 30 Lite]]
 +
* [[used by::Huawei P40 Lite]]
 +
* [[used by::Huawei Nova 7i]]
 +
* [[used by::Huawei nova 6 SE]]
 +
* [[used by::Huawei P smart Pro 2019]]
 +
* [[used by::Huawei nova 5z]]
 +
* [[used by::Huawei nova 5i Pro]]
 +
* [[used by::Huawei Honor 20S]]
 +
* [[used by::Huawei MatePad 10.4]]

Latest revision as of 22:23, 24 October 2021

Edit Values
Kirin 810
General Info
DesignerHiSilicon,
ARM Holdings
ManufacturerTSMC
Model Number810
MarketMobile
IntroductionJune 21, 2019 (announced)
June 21, 2019 (launched)
General Specs
FamilyKirin
Series800
Frequency2,270 MHz, 1,880 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A76, Cortex-A55
Core NameCortex-A76, Cortex-A55
Process7 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Multiprocessing
Max SMP1-Way (Uniprocessor)
Succession
k810.jpg

Kirin 810 is a 64-bit octa-core mid-range performance mobile ARM SoC introduced by HiSilicon in mid-2019. This chip, which is fabricated on TSMC's 7 nm process, features two Cortex-A76 big cores operating at up to 2.27 GHz along with six Cortex-A55 little cores operating at up to 1.88 GHz. The 810 incorporates ARM's Mali-G52 MP6 GPU.

Cache[edit]

Main articles: Cortex-A55 § Cache and Cortex-A76 § Cache


For the Cortex-A76:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
2x64 KiB  
L1D$128 KiB
131,072 B
0.125 MiB
2x64 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  2x512 KiB  

For the Cortex-A55:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$192 KiB
196,608 B
0.188 MiB
6x32 KiB  
L1D$192 KiB
196,608 B
0.188 MiB
6x32 KiB  
L2$768 KiB
0.75 MiB
786,432 B
7.324219e-4 GiB
  6x128 KiB  


Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-4266
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels4
Width16 bit
Max Bandwidth31.78 GiB/s
32,542.72 MiB/s
34.124 GB/s
34,123.515 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Double 15.89 GiB/s
Quad 31.78 GiB/s


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G52
DesignerARM Holdings
Execution Units6Max Displays2
Frequency850 MHz
0.85 GHz
850,000 KHz
Max Resolution
 2340x1080
Standards
DirectX12
OpenCL2.0
OpenGL ES3.2
OpenVG1.1
Vulkan1.0
  • Hardware Acceleration
    • Decode: 1080p @ 60fps
    • Encode: 1080p @ 30fps

NPU[edit]

This is the first neural processing unit to use their own homegrown NPU based on Hisilicon's first generation Da Vinci architecture. The NPU contains one processor core and a scheduling core.

ISP[edit]

  • 40 MP+ 24 MP dual

48 single

Wireless[edit]

  • LTE Modem
    • DL: Up to User Equipment (UE) category 12
      • Downlink of up to 600 Mbps
    • UL: Up to User Equipment (UE) category 13
      • Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
  • Wi-Fi 802.11 ac
  • Bluetooth 5
  • NFC
  • GPS / A-GPS / GLONASS / BDS

Location[edit]

  • GPS, AGPS, Glonass, Beidou

Utilizing devices[edit]

  • Huawei Nova 5
  • Huawei Honor 9x
  • Huawei Honor 9x Pro
  • Huawei Mate 30 Lite
  • Huawei P40 Lite
  • Huawei Nova 7i
  • Huawei nova 6 SE
  • Huawei P smart Pro 2019
  • Huawei nova 5z
  • Huawei nova 5i Pro
  • Huawei Honor 20S
  • Huawei MatePad 10.4
Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kirin/810&oldid=99401"
Facts about "Kirin 810 - HiSilicon"
RDF feed
base frequency2,270 MHz (2.27 GHz, 2,270,000 kHz) + and 1,880 MHz (1.88 GHz, 1,880,000 kHz) +
core count8 +
core nameCortex-A76 + and Cortex-A55 +
designerHiSilicon + and ARM Holdings +
familyKirin +
first announcedJune 21, 2019 +
first launchedJune 21, 2019 +
full page namehisilicon/kirin/810 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuMali-G52 +
integrated gpu base frequency850 MHz (0.85 GHz, 850,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units6 +
isaARMv8 +
isa familyARM +
l1$ size256 KiB (262,144 B, 0.25 MiB) + and 384 KiB (393,216 B, 0.375 MiB) +
l1d$ size128 KiB (131,072 B, 0.125 MiB) + and 192 KiB (196,608 B, 0.188 MiB) +
l1i$ size128 KiB (131,072 B, 0.125 MiB) + and 192 KiB (196,608 B, 0.188 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
ldateJune 21, 2019 +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory bandwidth31.78 GiB/s (32,542.72 MiB/s, 34.124 GB/s, 34,123.515 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels4 +
microarchitectureCortex-A76 + and Cortex-A55 +
model number810 +
nameKirin 810 +
process7 nm (0.007 μm, 7.0e-6 mm) +
series800 +
smp max ways1 +
supported memory typeLPDDR4X-4266 +
technologyCMOS +
thread count8 +
used byHuawei Nova 5 +, Huawei Honor 9x +, Huawei Honor 9x Pro +, Huawei Mate 30 Lite +, Huawei P40 Lite +, Huawei Nova 7i +, Huawei nova 6 SE +, Huawei P smart Pro 2019 +, Huawei nova 5z +, Huawei nova 5i Pro +, Huawei Honor 20S + and Huawei MatePad 10.4 +
word size64 bit (8 octets, 16 nibbles) +