From WikiChip
Difference between revisions of "intel/xeon platinum/8280m"
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{{chip | {{chip | ||
|name=Xeon Platinum 8280M | |name=Xeon Platinum 8280M | ||
− | |image= | + | |image=cascade lake sp (front).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=8280M | |model number=8280M | ||
+ | |part number=CD8069504228101 | ||
+ | |s-spec=SRF9Q | ||
+ | |s-spec qs=QRL0 | ||
|market=Server | |market=Server | ||
− | |first announced= | + | |first announced=April 2, 2019 |
− | |first launched= | + | |first launched=April 2, 2019 |
+ | |release price (tray)=$13,012.00 | ||
|family=Xeon Platinum | |family=Xeon Platinum | ||
− | |series= | + | |series=8200 |
+ | |locked=Yes | ||
|frequency=2,700 MHz | |frequency=2,700 MHz | ||
− | |turbo frequency1= | + | |turbo frequency1=4,000 MHz |
|clock multiplier=27 | |clock multiplier=27 | ||
|cpuid=0x50655 | |cpuid=0x50655 | ||
Line 22: | Line 27: | ||
|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
+ | |core stepping=B0 | ||
+ | |core stepping 2=B1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 27: | Line 34: | ||
|core count=28 | |core count=28 | ||
|thread count=56 | |thread count=56 | ||
+ | |max memory=2 TiB | ||
|max cpus=8 | |max cpus=8 | ||
+ | |smp interconnect=UPI | ||
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=205 W | |tdp=205 W | ||
− | |package | + | |package name 1=intel,fclga_3647 |
+ | |predecessor=Xeon Platinum 8180M | ||
+ | |predecessor link=intel/xeon_platinum/8180m | ||
}} | }} | ||
− | '''Xeon Platinum 8280M''' is a {{arch|64}} [[28-core]] [[x86]] | + | '''Xeon Platinum 8280M''' is a {{arch|64}} [[28-core]] [[x86]] high-performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Platinum 8280M is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 8-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 2 TiB of hexa-channel DDR4-2933 memory, operates at 2.7 GHz with a TDP of 205 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz. |
− | + | As indicated by the "''M''" suffix, this model features large memory support of up to 2 TiB of memory. | |
− | |||
Line 60: | Line 72: | ||
== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-2933 |
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem=2 TiB |
|controllers=2 | |controllers=2 | ||
|channels=6 | |channels=6 | ||
− | |max bandwidth= | + | |max bandwidth=131.13 GiB/s |
− | |bandwidth schan= | + | |bandwidth schan=21.86 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=43.71 GiB/s |
− | |bandwidth qchan= | + | |bandwidth qchan=87.42 GiB/s |
− | |bandwidth hchan= | + | |bandwidth hchan=131.13 GiB/s |
}} | }} | ||
== Expansions == | == Expansions == | ||
− | {{expansions | + | {{expansions main |
− | | pcie revision | + | | |
− | | pcie lanes | + | {{expansions entry |
− | | pcie config | + | |type=PCIe |
− | | pcie config 2 | + | |pcie revision=3.0 |
− | | pcie config 3 | + | |pcie lanes=48 |
+ | |pcie config=1x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
}} | }} | ||
Line 115: | Line 131: | ||
|avx5124vnniw=No | |avx5124vnniw=No | ||
|avx512vpopcntdq=No | |avx512vpopcntdq=No | ||
+ | |avx512units=2 | ||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
Line 181: | Line 198: | ||
|amdpb2=No | |amdpb2=No | ||
|amdpbod=No | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,700MHz | ||
+ | |freq_1=4,000MHz | ||
+ | |freq_2=4,000MHz | ||
+ | |freq_3=3,800MHz | ||
+ | |freq_4=3,800MHz | ||
+ | |freq_5=3,700MHz | ||
+ | |freq_6=3,700MHz | ||
+ | |freq_7=3,700MHz | ||
+ | |freq_8=3,700MHz | ||
+ | |freq_9=3,700MHz | ||
+ | |freq_10=3,700MHz | ||
+ | |freq_11=3,700MHz | ||
+ | |freq_12=3,700MHz | ||
+ | |freq_13=3,700MHz | ||
+ | |freq_14=3,700MHz | ||
+ | |freq_15=3,700MHz | ||
+ | |freq_16=3,700MHz | ||
+ | |freq_17=3,700MHz | ||
+ | |freq_18=3,700MHz | ||
+ | |freq_19=3,700MHz | ||
+ | |freq_20=3,700MHz | ||
+ | |freq_21=3,500MHz | ||
+ | |freq_22=3,500MHz | ||
+ | |freq_23=3,500MHz | ||
+ | |freq_24=3,500MHz | ||
+ | |freq_25=3,300MHz | ||
+ | |freq_26=3,300MHz | ||
+ | |freq_27=3,300MHz | ||
+ | |freq_28=3,300MHz | ||
+ | |freq_avx2_base=2,200MHz | ||
+ | |freq_avx2_1=3,800MHz | ||
+ | |freq_avx2_2=3,800MHz | ||
+ | |freq_avx2_3=3,600MHz | ||
+ | |freq_avx2_4=3,600MHz | ||
+ | |freq_avx2_5=3,500MHz | ||
+ | |freq_avx2_6=3,500MHz | ||
+ | |freq_avx2_7=3,500MHz | ||
+ | |freq_avx2_8=3,500MHz | ||
+ | |freq_avx2_9=3,500MHz | ||
+ | |freq_avx2_10=3,500MHz | ||
+ | |freq_avx2_11=3,500MHz | ||
+ | |freq_avx2_12=3,500MHz | ||
+ | |freq_avx2_13=3,500MHz | ||
+ | |freq_avx2_14=3,500MHz | ||
+ | |freq_avx2_15=3,500MHz | ||
+ | |freq_avx2_16=3,500MHz | ||
+ | |freq_avx2_17=3,300MHz | ||
+ | |freq_avx2_18=3,300MHz | ||
+ | |freq_avx2_19=3,300MHz | ||
+ | |freq_avx2_20=3,300MHz | ||
+ | |freq_avx2_21=3,000MHz | ||
+ | |freq_avx2_22=3,000MHz | ||
+ | |freq_avx2_23=3,000MHz | ||
+ | |freq_avx2_24=3,000MHz | ||
+ | |freq_avx2_25=2,900MHz | ||
+ | |freq_avx2_26=2,900MHz | ||
+ | |freq_avx2_27=2,900MHz | ||
+ | |freq_avx2_28=2,900MHz | ||
+ | |freq_avx512_base=1,800MHz | ||
+ | |freq_avx512_1=3,700MHz | ||
+ | |freq_avx512_2=3,700MHz | ||
+ | |freq_avx512_3=3,500MHz | ||
+ | |freq_avx512_4=3,500MHz | ||
+ | |freq_avx512_5=3,400MHz | ||
+ | |freq_avx512_6=3,400MHz | ||
+ | |freq_avx512_7=3,400MHz | ||
+ | |freq_avx512_8=3,400MHz | ||
+ | |freq_avx512_9=3,300MHz | ||
+ | |freq_avx512_10=3,300MHz | ||
+ | |freq_avx512_11=3,300MHz | ||
+ | |freq_avx512_12=3,300MHz | ||
+ | |freq_avx512_13=2,900MHz | ||
+ | |freq_avx512_14=2,900MHz | ||
+ | |freq_avx512_15=2,900MHz | ||
+ | |freq_avx512_16=2,900MHz | ||
+ | |freq_avx512_17=2,700MHz | ||
+ | |freq_avx512_18=2,700MHz | ||
+ | |freq_avx512_19=2,700MHz | ||
+ | |freq_avx512_20=2,700MHz | ||
+ | |freq_avx512_21=2,500MHz | ||
+ | |freq_avx512_22=2,500MHz | ||
+ | |freq_avx512_23=2,500MHz | ||
+ | |freq_avx512_24=2,500MHz | ||
+ | |freq_avx512_25=2,400MHz | ||
+ | |freq_avx512_26=2,400MHz | ||
+ | |freq_avx512_27=2,400MHz | ||
+ | |freq_avx512_28=2,400MHz | ||
}} | }} |
Latest revision as of 02:27, 2 March 2020
Edit Values | |
Xeon Platinum 8280M | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 8280M |
Part Number | CD8069504228101 |
S-Spec | SRF9Q QRL0 (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $13,012.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon Platinum |
Series | 8200 |
Locked | Yes |
Frequency | 2,700 MHz |
Turbo Frequency | 4,000 MHz (1 core) |
Clock multiplier | 27 |
CPUID | 0x50655 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Stepping | B0, B1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 28 |
Threads | 56 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 8-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 205 W |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Platinum 8280M is a 64-bit 28-core x86 high-performance server microprocessor introduced by Intel in early 2019. The Platinum 8280M is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 8-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 2 TiB of hexa-channel DDR4-2933 memory, operates at 2.7 GHz with a TDP of 205 W and features a turbo boost frequency of up to 4.0 GHz.
As indicated by the "M" suffix, this model features large memory support of up to 2 TiB of memory.
Cache[edit]
- Main article: Cascade Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | ||
Normal | 2,700MHz | 4,000MHz | 4,000MHz | 3,800MHz | 3,800MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,700MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz |
AVX2 | 2,200MHz | 3,800MHz | 3,800MHz | 3,600MHz | 3,600MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,000MHz | 3,000MHz | 3,000MHz | 3,000MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,900MHz |
AVX512 | 1,800MHz | 3,700MHz | 3,700MHz | 3,500MHz | 3,500MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,700MHz | 2,700MHz | 2,700MHz | 2,700MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,400MHz | 2,400MHz | 2,400MHz | 2,400MHz |
Facts about "Xeon Platinum 8280M - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Platinum 8280M - Intel#pcie + |
base frequency | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 27 + |
core count | 28 + |
core family | 6 + |
core name | Cascade Lake SP + |
core stepping | B0 + and B1 + |
cpuid | 0x50655 + |
designer | Intel + |
family | Xeon Platinum + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon platinum/8280m + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,792 KiB (1,835,008 B, 1.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 28 MiB (28,672 KiB, 29,360,128 B, 0.0273 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 38.5 MiB (39,424 KiB, 40,370,176 B, 0.0376 GiB) + |
ldate | April 2, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max cpu count | 8 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
model number | 8280M + |
name | Xeon Platinum 8280M + |
number of avx-512 execution units | 2 + |
package | FCLGA-3647 + |
part number | CD8069504228101 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 13,012.00 (€ 11,710.80, £ 10,539.72, ¥ 1,344,529.96) + |
release price (tray) | $ 13,012.00 (€ 11,710.80, £ 10,539.72, ¥ 1,344,529.96) + |
s-spec | SRF9Q + |
s-spec (qs) | QRL0 + |
series | 8200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 8 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2933 + |
tdp | 205 W (205,000 mW, 0.275 hp, 0.205 kW) + |
technology | CMOS + |
thread count | 56 + |
turbo frequency (1 core) | 4,000 MHz (4 GHz, 4,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |