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Difference between revisions of "intel/xeon platinum/8280m"
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{{chip
 
{{chip
 
|name=Xeon Platinum 8280M
 
|name=Xeon Platinum 8280M
−
|image=skylake sp (basic).png
+
|image=cascade lake sp (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=8280M
 
|model number=8280M
 +
|part number=CD8069504228101
 +
|s-spec=SRF9Q
 +
|s-spec qs=QRL0
 
|market=Server
 
|market=Server
−
|first announced=December 2018
+
|first announced=April 2, 2019
−
|first launched=December 2018
+
|first launched=April 2, 2019
 +
|release price (tray)=$13,012.00
 
|family=Xeon Platinum
 
|family=Xeon Platinum
−
|series=8000
+
|series=8200
 +
|locked=Yes
 
|frequency=2,700 MHz
 
|frequency=2,700 MHz
−
|turbo frequency1=3,900 MHz
+
|turbo frequency1=4,000 MHz
 
|clock multiplier=27
 
|clock multiplier=27
 
|cpuid=0x50655
 
|cpuid=0x50655
Line 22: Line 27:
 
|core name=Cascade Lake SP
 
|core name=Cascade Lake SP
 
|core family=6
 
|core family=6
 +
|core stepping=B0
 +
|core stepping 2=B1
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
Line 27: Line 34:
 
|core count=28
 
|core count=28
 
|thread count=56
 
|thread count=56
 +
|max memory=2 TiB
 
|max cpus=8
 
|max cpus=8
 +
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 
|tdp=205 W
 
|tdp=205 W
−
|package module 1={{packages/intel/fclga-3647}}
+
|package name 1=intel,fclga_3647
 +
|predecessor=Xeon Platinum 8180M
 +
|predecessor link=intel/xeon_platinum/8180m
 
}}
 
}}
−
'''Xeon Platinum 8280M''' is a {{arch|64}} [[28-core]] [[x86]] multi-socket highest performance server microprocessor planned by [[Intel]] for late 2018. This chip supports up to 8-way multiprocessing. The Platinum 8280M, which is based on the server configuration of the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm++ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.7 GHz with a TDP of 205 W and a {{intel|turbo boost}} frequency of up to ? GHz, supports up ? GiB of hexa-channel DDR4-2666 memory.
+
'''Xeon Platinum 8280M''' is a {{arch|64}} [[28-core]] [[x86]] high-performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Platinum 8280M is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 8-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 2 TiB of hexa-channel DDR4-2933 memory, operates at 2.7 GHz with a TDP of 205 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz.
  
−
 
+
As indicated by the "''M''" suffix, this model features large memory support of up to 2 TiB of memory.
−
{{unknown features}}
 
  
  
Line 60: Line 72:
 
== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=DDR4-2666
+
|type=DDR4-2933
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=? GiB
+
|max mem=2 TiB
 
|controllers=2
 
|controllers=2
 
|channels=6
 
|channels=6
−
|max bandwidth=119.21 GiB/s
+
|max bandwidth=131.13 GiB/s
−
|bandwidth schan=19.87 GiB/s
+
|bandwidth schan=21.86 GiB/s
−
|bandwidth dchan=39.74 GiB/s
+
|bandwidth dchan=43.71 GiB/s
−
|bandwidth qchan=79.47 GiB/s
+
|bandwidth qchan=87.42 GiB/s
−
|bandwidth hchan=119.21 GiB/s
+
|bandwidth hchan=131.13 GiB/s
 
}}
 
}}
  
 
== Expansions ==
 
== Expansions ==
−
{{expansions
+
{{expansions main
−
| pcie revision     = 3.0
+
|
−
| pcie lanes         = 48
+
{{expansions entry
−
| pcie config       = x16
+
|type=PCIe
−
| pcie config 2     = x8
+
|pcie revision=3.0
−
| pcie config 3     = x4
+
|pcie lanes=48
 +
|pcie config=1x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 
}}
 
}}
  
Line 112: Line 128:
 
|avx512vbmi=No
 
|avx512vbmi=No
 
|avx5124fmaps=No
 
|avx5124fmaps=No
 +
|avx512vnni=Yes
 
|avx5124vnniw=No
 
|avx5124vnniw=No
 
|avx512vpopcntdq=No
 
|avx512vpopcntdq=No
 +
|avx512units=2
 
|abm=Yes
 
|abm=Yes
 
|tbm=No
 
|tbm=No
Line 127: Line 145:
 
|clmul=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|f16c=Yes
 +
|bfloat16=No
 
|tbt1=No
 
|tbt1=No
 
|tbt2=Yes
 
|tbt2=Yes
Line 159: Line 178:
 
|securekey=No
 
|securekey=No
 
|osguard=No
 
|osguard=No
 +
|intqat=No
 +
|dlboost=Yes
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
Line 172: Line 193:
 
|sensemi=No
 
|sensemi=No
 
|xfr=No
 
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,700MHz
 +
|freq_1=4,000MHz
 +
|freq_2=4,000MHz
 +
|freq_3=3,800MHz
 +
|freq_4=3,800MHz
 +
|freq_5=3,700MHz
 +
|freq_6=3,700MHz
 +
|freq_7=3,700MHz
 +
|freq_8=3,700MHz
 +
|freq_9=3,700MHz
 +
|freq_10=3,700MHz
 +
|freq_11=3,700MHz
 +
|freq_12=3,700MHz
 +
|freq_13=3,700MHz
 +
|freq_14=3,700MHz
 +
|freq_15=3,700MHz
 +
|freq_16=3,700MHz
 +
|freq_17=3,700MHz
 +
|freq_18=3,700MHz
 +
|freq_19=3,700MHz
 +
|freq_20=3,700MHz
 +
|freq_21=3,500MHz
 +
|freq_22=3,500MHz
 +
|freq_23=3,500MHz
 +
|freq_24=3,500MHz
 +
|freq_25=3,300MHz
 +
|freq_26=3,300MHz
 +
|freq_27=3,300MHz
 +
|freq_28=3,300MHz
 +
|freq_avx2_base=2,200MHz
 +
|freq_avx2_1=3,800MHz
 +
|freq_avx2_2=3,800MHz
 +
|freq_avx2_3=3,600MHz
 +
|freq_avx2_4=3,600MHz
 +
|freq_avx2_5=3,500MHz
 +
|freq_avx2_6=3,500MHz
 +
|freq_avx2_7=3,500MHz
 +
|freq_avx2_8=3,500MHz
 +
|freq_avx2_9=3,500MHz
 +
|freq_avx2_10=3,500MHz
 +
|freq_avx2_11=3,500MHz
 +
|freq_avx2_12=3,500MHz
 +
|freq_avx2_13=3,500MHz
 +
|freq_avx2_14=3,500MHz
 +
|freq_avx2_15=3,500MHz
 +
|freq_avx2_16=3,500MHz
 +
|freq_avx2_17=3,300MHz
 +
|freq_avx2_18=3,300MHz
 +
|freq_avx2_19=3,300MHz
 +
|freq_avx2_20=3,300MHz
 +
|freq_avx2_21=3,000MHz
 +
|freq_avx2_22=3,000MHz
 +
|freq_avx2_23=3,000MHz
 +
|freq_avx2_24=3,000MHz
 +
|freq_avx2_25=2,900MHz
 +
|freq_avx2_26=2,900MHz
 +
|freq_avx2_27=2,900MHz
 +
|freq_avx2_28=2,900MHz
 +
|freq_avx512_base=1,800MHz
 +
|freq_avx512_1=3,700MHz
 +
|freq_avx512_2=3,700MHz
 +
|freq_avx512_3=3,500MHz
 +
|freq_avx512_4=3,500MHz
 +
|freq_avx512_5=3,400MHz
 +
|freq_avx512_6=3,400MHz
 +
|freq_avx512_7=3,400MHz
 +
|freq_avx512_8=3,400MHz
 +
|freq_avx512_9=3,300MHz
 +
|freq_avx512_10=3,300MHz
 +
|freq_avx512_11=3,300MHz
 +
|freq_avx512_12=3,300MHz
 +
|freq_avx512_13=2,900MHz
 +
|freq_avx512_14=2,900MHz
 +
|freq_avx512_15=2,900MHz
 +
|freq_avx512_16=2,900MHz
 +
|freq_avx512_17=2,700MHz
 +
|freq_avx512_18=2,700MHz
 +
|freq_avx512_19=2,700MHz
 +
|freq_avx512_20=2,700MHz
 +
|freq_avx512_21=2,500MHz
 +
|freq_avx512_22=2,500MHz
 +
|freq_avx512_23=2,500MHz
 +
|freq_avx512_24=2,500MHz
 +
|freq_avx512_25=2,400MHz
 +
|freq_avx512_26=2,400MHz
 +
|freq_avx512_27=2,400MHz
 +
|freq_avx512_28=2,400MHz
 
}}
 
}}

Latest revision as of 02:27, 2 March 2020

Edit Values
Xeon Platinum 8280M
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number8280M
Part NumberCD8069504228101
S-SpecSRF9Q
QRL0 (QS)
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$13,012.00 (tray)
ShopAmazon
General Specs
FamilyXeon Platinum
Series8200
LockedYes
Frequency2,700 MHz
Turbo Frequency4,000 MHz (1 core)
Clock multiplier27
CPUID0x50655
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core SteppingB0, B1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores28
Threads56
Max Memory2 TiB
Multiprocessing
Max SMP8-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP205 W
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Platinum 8280M is a 64-bit 28-core x86 high-performance server microprocessor introduced by Intel in early 2019. The Platinum 8280M is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 8-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 2 TiB of hexa-channel DDR4-2933 memory, operates at 2.7 GHz with a TDP of 205 W and features a turbo boost frequency of up to 4.0 GHz.

As indicated by the "M" suffix, this model features large memory support of up to 2 TiB of memory.


Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.75 MiB
1,792 KiB
1,835,008 B
L1I$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associative 
L1D$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associativewrite-back
L2$28 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
  28x1 MiB16-way set associativewrite-back
L3$38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
  28x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem2 TiB
Controllers2
Channels6
Max Bandwidth131.13 GiB/s
134,277.12 MiB/s
140.8 GB/s
140,799.765 MB/s
0.128 TiB/s
0.141 TB/s
Bandwidth
Single 21.86 GiB/s
Double 43.71 GiB/s
Quad 87.42 GiB/s
Hexa 131.13 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (2 Units)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support
DL BoostDeep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678910111213141516171819202122232425262728
Normal2,700MHz4,000MHz4,000MHz3,800MHz3,800MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,700MHz3,500MHz3,500MHz3,500MHz3,500MHz3,300MHz3,300MHz3,300MHz3,300MHz
AVX22,200MHz3,800MHz3,800MHz3,600MHz3,600MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,500MHz3,300MHz3,300MHz3,300MHz3,300MHz3,000MHz3,000MHz3,000MHz3,000MHz2,900MHz2,900MHz2,900MHz2,900MHz
AVX5121,800MHz3,700MHz3,700MHz3,500MHz3,500MHz3,400MHz3,400MHz3,400MHz3,400MHz3,300MHz3,300MHz3,300MHz3,300MHz2,900MHz2,900MHz2,900MHz2,900MHz2,700MHz2,700MHz2,700MHz2,700MHz2,500MHz2,500MHz2,500MHz2,500MHz2,400MHz2,400MHz2,400MHz2,400MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_platinum/8280m&oldid=96313"
Facts about "Xeon Platinum 8280M - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Platinum 8280M - Intel#io +
base frequency2,700 MHz (2.7 GHz, 2,700,000 kHz) +
chipsetLewisburg +
clock multiplier27 +
core count28 +
core family6 +
core nameCascade Lake SP +
cpuid0x50655 +
designerIntel +
familyXeon Platinum +
first announcedDecember 2018 +
first launchedDecember 2018 +
full page nameintel/xeon platinum/8280m +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,792 KiB (1,835,008 B, 1.75 MiB) +
l1d$ description8-way set associative +
l1d$ size896 KiB (917,504 B, 0.875 MiB) +
l1i$ description8-way set associative +
l1i$ size896 KiB (917,504 B, 0.875 MiB) +
l2$ description16-way set associative +
l2$ size28 MiB (28,672 KiB, 29,360,128 B, 0.0273 GiB) +
l3$ description11-way set associative +
l3$ size38.5 MiB (39,424 KiB, 40,370,176 B, 0.0376 GiB) +
ldateDecember 2018 +
main imageFile:skylake sp (basic).png +
manufacturerIntel +
market segmentServer +
max cpu count8 +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureCascade Lake +
model number8280M +
nameXeon Platinum 8280M +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
series8000 +
smp max ways8 +
supported memory typeDDR4-2666 +
tdp205 W (205,000 mW, 0.275 hp, 0.205 kW) +
technologyCMOS +
thread count56 +
turbo frequency (1 core)3,900 MHz (3.9 GHz, 3,900,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +