From WikiChip
Difference between revisions of "intel/cores/cascade lake ap"
(16 intermediate revisions by 2 users not shown) | |||
Line 2: | Line 2: | ||
{{core | {{core | ||
|name=Cascade Lake AP | |name=Cascade Lake AP | ||
− | | | + | |image=cascade lake ap (front).png |
|developer=Intel | |developer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
Line 13: | Line 13: | ||
|package name 1=intel,fcbga_5903 | |package name 1=intel,fcbga_5903 | ||
}} | }} | ||
− | '''Cascade Lake AP''' ('''Cascade Lake Advanced Performance''') is code name for a series of high core-count multi-chip packaged server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture part of the {{intel|Walker Pass|l=platform}} platform. | + | '''Cascade Lake AP''' ('''CLX-AP''', '''Cascade Lake Advanced Performance''') is code name for a series of high core-count multi-chip packaged server [[multiprocessors]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture part of the {{intel|Walker Pass|l=platform}} platform. |
+ | Cascade Lake AP-based processors are branded as {{intel|Xeon Platinum}} 9200-series. | ||
− | {{ | + | == Overview == |
+ | Cascade Lake AP comprise of two {{intel|Cascade Lake|l=arch}} dies packaged together a single BGA-5903 substrate. Those processors support up to 56 cores, 112 threads, and up to 12 DDR4 channels. | ||
− | + | Cascade Lake AP processors cannot be purchased individually. Instead, they can only be bought as part of the S9200WK compute module (essentially a complete system designed by Intel). | |
− | |||
− | Cascade Lake AP | ||
=== Common Features === | === Common Features === | ||
* 12-channel memory | * 12-channel memory | ||
− | ** UP to DDR4- | + | ** UP to DDR4-2933 MT/s |
** ECC support | ** ECC support | ||
− | * '''TDP:''' | + | * '''TDP:''' 250 W to 400 W |
− | * '''PCIe:''' | + | * '''PCIe:''' x40 Lanes of PCIe Gen 3 (limited by the S9200WK module, actual models support more lanes but are not sold independently) |
− | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL, AVX512VNNI) | + | * '''ISA:''' Everything up to {{x86|AVX-512}} (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, {{x86|AVX512DQ}}, {{x86|AVX512VL}}, {{x86|AVX512VNNI}}) |
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}} | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}} | ||
{{clear}} | {{clear}} | ||
− | == Cascade Lake AP Processors == | + | == Cascade Lake AP Processors== |
− | {{ | + | <!-- NOTE: |
+ | This table is generated automatically from the data in the actual articles. | ||
+ | If a microprocessor is missing from the list, an appropriate article for it needs to be | ||
+ | created and tagged accordingly. | ||
+ | |||
+ | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips | ||
+ | --> | ||
+ | {{comp table start}} | ||
+ | <table class="comptable sortable tc3 tc4 tc5 tc6 tc7 tc8"> | ||
+ | {{comp table header|main|11:List of Cascade Lake AP-based Processors}} | ||
+ | {{comp table header|cols|Launched|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo}} | ||
+ | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]] | ||
+ | |?full page name | ||
+ | |?model number | ||
+ | |?first launched | ||
+ | |?core count | ||
+ | |?thread count | ||
+ | |?tdp | ||
+ | |?l2$ size | ||
+ | |?l3$ size | ||
+ | |?base frequency#GHz | ||
+ | |?turbo frequency (1 core)#GHz | ||
+ | |format=template | ||
+ | |template=proc table 3 | ||
+ | |userparam=10 | ||
+ | |sort=model number | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | {{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]]}} | ||
+ | </table> | ||
+ | {{comp table end}} | ||
+ | |||
+ | === SKU Comparison === | ||
+ | Below are a number of SKU comparison graphs based on their specifications. | ||
+ | |||
+ | <div style="float: left; margin: 10px"> | ||
+ | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]] | ||
+ | |?core count | ||
+ | |?base frequency | ||
+ | |charttitle=Cores vs. Base Frequency | ||
+ | |numbersaxislabel=Frequency (MHz) | ||
+ | |labelaxislabel=Core Count | ||
+ | |height=400 | ||
+ | |width=400 | ||
+ | |theme=vector | ||
+ | |group=property | ||
+ | |grouplabel=subject | ||
+ | |charttype=scatter | ||
+ | |format=jqplotseries | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | </div> | ||
+ | |||
+ | <div style="float: left; margin: 10px"> | ||
+ | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]] | ||
+ | |?core count | ||
+ | |?turbo frequency (1 core) | ||
+ | |charttitle=Cores vs. Turbo Frequency | ||
+ | |numbersaxislabel=Frequency (MHz) | ||
+ | |labelaxislabel=Core Count | ||
+ | |height=400 | ||
+ | |width=400 | ||
+ | |theme=vector | ||
+ | |group=property | ||
+ | |grouplabel=subject | ||
+ | |charttype=scatter | ||
+ | |format=jqplotseries | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | </div> | ||
+ | |||
+ | <div style="float: left; margin: 10px"> | ||
+ | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]] | ||
+ | |?core count | ||
+ | |?tdp | ||
+ | |charttitle=Cores vs. TDP | ||
+ | |numbersaxislabel=TDP (W) | ||
+ | |labelaxislabel=Core Count | ||
+ | |height=400 | ||
+ | |width=400 | ||
+ | |theme=vector | ||
+ | |group=property | ||
+ | |grouplabel=subject | ||
+ | |charttype=scatter | ||
+ | |format=jqplotseries | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | </div> | ||
+ | |||
+ | <div style="float: left; margin: 10px"> | ||
+ | {{#ask: [[Category:microprocessor models by intel]] [[core name::Cascade Lake AP]] | ||
+ | |?turbo frequency (1 core) | ||
+ | |?tdp | ||
+ | |charttitle=Frequency vs. TDP | ||
+ | |numbersaxislabel=TDP (W) | ||
+ | |labelaxislabel=Frequency (MHz) | ||
+ | |height=400 | ||
+ | |width=400 | ||
+ | |theme=vector | ||
+ | |group=property | ||
+ | |grouplabel=subject | ||
+ | |charttype=scatter | ||
+ | |format=jqplotseries | ||
+ | |mainlabel=- | ||
+ | }} | ||
+ | </div> | ||
+ | |||
+ | {{clear}} | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:S9200WK-Reference-Design-Guide.pdf|S9200WK reference design guide]] | ||
== See also == | == See also == | ||
{{intel cascade lake core see also}} | {{intel cascade lake core see also}} |
Latest revision as of 17:46, 1 February 2020
Edit Values | |
Cascade Lake AP | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Microarchitecture | |
ISA | x86-64 |
Microarchitecture | Cascade Lake |
Platform | Walker Pass |
Word Size | 8 octets 64 bit16 nibbles |
Process | 14 nm 0.014 μm 1.4e-5 mm |
Technology | CMOS |
Packaging | |
Package | FCBGA-5903 (BGA) |
Pitch | 0.99 mm |
Contacts | 5903 |
Cascade Lake AP (CLX-AP, Cascade Lake Advanced Performance) is code name for a series of high core-count multi-chip packaged server multiprocessors based on the Cascade Lake microarchitecture part of the Walker Pass platform.
Cascade Lake AP-based processors are branded as Xeon Platinum 9200-series.
Contents
Overview[edit]
Cascade Lake AP comprise of two Cascade Lake dies packaged together a single BGA-5903 substrate. Those processors support up to 56 cores, 112 threads, and up to 12 DDR4 channels.
Cascade Lake AP processors cannot be purchased individually. Instead, they can only be bought as part of the S9200WK compute module (essentially a complete system designed by Intel).
Common Features[edit]
- 12-channel memory
- UP to DDR4-2933 MT/s
- ECC support
- TDP: 250 W to 400 W
- PCIe: x40 Lanes of PCIe Gen 3 (limited by the S9200WK module, actual models support more lanes but are not sold independently)
- ISA: Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL, AVX512VNNI)
- Features: Speed Shift, vPro, VT-x, TSX, TXT
Cascade Lake AP Processors[edit]
List of Cascade Lake AP-based Processors | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
Model | Launched | Cores | Threads | TDP | L2 | L3 | Frequency | Turbo | |||
9221 | 2 April 2019 | 32 | 64 | 250 W 250,000 mW 0.335 hp 0.25 kW | 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB | 71.5 MiB 73,216 KiB 74,973,184 B 0.0698 GiB | 2.1 GHz 2,100 MHz 2,100,000 kHz | 3.7 GHz 3,700 MHz 3,700,000 kHz | |||
9222 | 2 April 2019 | 32 | 64 | 250 W 250,000 mW 0.335 hp 0.25 kW | 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB | 71.5 MiB 73,216 KiB 74,973,184 B 0.0698 GiB | 2.3 GHz 2,300 MHz 2,300,000 kHz | 3.7 GHz 3,700 MHz 3,700,000 kHz | |||
9242 | 2 April 2019 | 48 | 96 | 350 W 350,000 mW 0.469 hp 0.35 kW | 48 MiB 49,152 KiB 50,331,648 B 0.0469 GiB | 71.5 MiB 73,216 KiB 74,973,184 B 0.0698 GiB | 2.3 GHz 2,300 MHz 2,300,000 kHz | 3.8 GHz 3,800 MHz 3,800,000 kHz | |||
9282 | 2 April 2019 | 56 | 112 | 400 W 400,000 mW 0.536 hp 0.4 kW | 56 MiB 57,344 KiB 58,720,256 B 0.0547 GiB | 77 MiB 78,848 KiB 80,740,352 B 0.0752 GiB | 2.6 GHz 2,600 MHz 2,600,000 kHz | 3.8 GHz 3,800 MHz 3,800,000 kHz | |||
Count: 4 |
SKU Comparison[edit]
Below are a number of SKU comparison graphs based on their specifications.
Loading...
Loading...
Loading...
Loading...
Documents[edit]
See also[edit]
|
Facts about "Cascade Lake AP - Cores - Intel"
designer | Intel + |
instance of | core + |
isa | x86-64 + |
main image | + |
manufacturer | Intel + |
microarchitecture | Cascade Lake + |
name | Cascade Lake AP + |
package | FCBGA-5903 + |
platform | Walker Pass + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |