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Difference between revisions of "umich/microarchitectures/celerity"
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'''Celerity''' is a custom [[RISC-V]]-based [[neural processor]] microarchitecture. The work is a joint effort by the Bespoke Silicon Group at the University of Washington, Cornell University, University of Michigan, and UC San Diego. | '''Celerity''' is a custom [[RISC-V]]-based [[neural processor]] microarchitecture. The work is a joint effort by the Bespoke Silicon Group at the University of Washington, Cornell University, University of Michigan, and UC San Diego. | ||
| + | |||
| + | == Process technology == | ||
| + | Celerity is fabricated on [[TSMC]] [[16 nm process]]. | ||
| + | |||
| + | == Overview == | ||
| + | {{empty section}} | ||
| + | |||
| + | == Compute tiers == | ||
| + | {{empty section}} | ||
| + | === General-purpose tier === | ||
| + | {{empty section}} | ||
| + | === Massively parallel tier === | ||
| + | {{empty section}} | ||
| + | === Specialization tier === | ||
| + | {{empty section}} | ||
| + | |||
| + | == Die == | ||
| + | {{empty section}} | ||
== Bibliography == | == Bibliography == | ||
* {{bib|vlsi|2019}} | * {{bib|vlsi|2019}} | ||
* {{bib|hc|29}} | * {{bib|hc|29}} | ||
Revision as of 21:58, 20 January 2020
| Edit Values | |
| Celerity µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | University of Michigan, University of Washington, Cornell University, University of California |
| Manufacturer | TSMC |
| Process | 16 nm |
| Instructions | |
| ISA | RISC-V |
| Extensions | Integer, Multiply |
Celerity is a custom RISC-V-based neural processor microarchitecture. The work is a joint effort by the Bespoke Silicon Group at the University of Washington, Cornell University, University of Michigan, and UC San Diego.
Contents
Process technology
Celerity is fabricated on TSMC 16 nm process.
Overview
 |
This section is empty; you can help add the missing info by editing this page. |
Compute tiers
| |
This section is empty; you can help add the missing info by editing this page. |
General-purpose tier
| |
This section is empty; you can help add the missing info by editing this page. |
Massively parallel tier
| |
This section is empty; you can help add the missing info by editing this page. |
Specialization tier
| |
This section is empty; you can help add the missing info by editing this page. |
Die
| |
This section is empty; you can help add the missing info by editing this page. |
Bibliography
- 2019 Symposia on VLSI Technology and Circuits (VLSI 2019).
- IEEE Hot Chips 29 Symposium (HCS) 2017.
Categories:
- cpu microarchitectures by university of michigan
- microarchitectures by university of michigan
- microarchitectures by university of washington
- cpu microarchitectures by university of washington
- microarchitectures by cornell university
- cpu microarchitectures by cornell university
- microarchitectures by university of california
- cpu microarchitectures by university of california
- all microarchitectures
Facts about "Celerity - Microarchitectures"
| codename | Celerity + |
| designer | University of Michigan +, University of Washington +, Cornell University + and University of California + |
| full page name | umich/microarchitectures/celerity + |
| instance of | microarchitecture + |
| instruction set architecture | RISC-V + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Celerity + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |