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Difference between revisions of "intel/xeon gold/6262v"
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(Created page with "{{intel title|Xeon Gold 6262V}} {{chip}} '''Xeon Gold 6262V''' is a {{arch|64}} 24-core x86 multi-socket high performance server microprocessor introduced by Intel...")
 
 
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{{intel title|Xeon Gold 6262V}}
 
{{intel title|Xeon Gold 6262V}}
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{{chip}}
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{{chip
−
'''Xeon Gold 6262V''' is a {{arch|64}} [[24-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6262V is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 8-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 1.9 GHz with a TDP of 135 W and features a {{intel|turbo boost}} frequency of up to 3.6 GHz.
+
|name=Xeon Gold 6262V
 +
|image=cascade lake sp (front).png
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|model number=6262V
 +
|s-spec qs=QS2B
 +
|market=Server
 +
|first announced=April 2, 2019
 +
|first launched=April 2, 2019
 +
|release price (tray)=$2,900.00
 +
|family=Xeon Gold
 +
|series=6200
 +
|locked=Yes
 +
|frequency=1,900 MHz
 +
|turbo frequency1=3,600 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=19
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Cascade Lake
 +
|platform=Purley
 +
|chipset=Lewisburg
 +
|core name=Cascade Lake SP
 +
|core family=6
 +
|core model=85
 +
|core stepping=B1
 +
|process=14 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=24
 +
|thread count=48
 +
|max memory=1 TiB
 +
|max cpus=4
 +
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 +
|tdp=135 W
 +
|tcase min=0 °C
 +
|tcase max=91 °C
 +
|package name 1=intel,fclga_3647
 +
}}
 +
'''Xeon Gold 6262V''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6262V is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 1.9 GHz with a TDP of 135 W and features a {{intel|turbo boost}} frequency of up to 3.6 GHz.
 +
 
 +
 
 +
 
 +
== Cache ==
 +
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 +
{{cache size
 +
|l1 cache=1.5 MiB
 +
|l1i cache=768 KiB
 +
|l1i break=24x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=768 KiB
 +
|l1d break=24x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=24 MiB
 +
|l2 break=24x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=33 MiB
 +
|l3 break=24x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2400
 +
|ecc=Yes
 +
|max mem=1 TiB
 +
|controllers=2
 +
|channels=6
 +
|max bandwidth=107.3 GiB/s
 +
|bandwidth schan=17.88 GiB/s
 +
|bandwidth dchan=35.76 GiB/s
 +
|bandwidth qchan=71.53 GiB/s
 +
|bandwidth hchan=107.3 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=48
 +
|pcie config=1x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=Yes
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=No
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=Yes
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=1,900MHz
 +
|freq_1=3,600MHz
 +
|freq_2=3,600MHz
 +
|freq_3=3,400MHz
 +
|freq_4=3,400MHz
 +
|freq_5=3,300MHz
 +
|freq_6=3,300MHz
 +
|freq_7=3,300MHz
 +
|freq_8=3,300MHz
 +
|freq_9=3,200MHz
 +
|freq_10=3,200MHz
 +
|freq_11=3,200MHz
 +
|freq_12=3,200MHz
 +
|freq_13=2,900MHz
 +
|freq_14=2,900MHz
 +
|freq_15=2,900MHz
 +
|freq_16=2,900MHz
 +
|freq_17=2,600MHz
 +
|freq_18=2,600MHz
 +
|freq_19=2,600MHz
 +
|freq_20=2,600MHz
 +
|freq_21=2,500MHz
 +
|freq_22=2,500MHz
 +
|freq_23=2,500MHz
 +
|freq_24=2,500MHz
 +
|freq_avx2_base=1,600MHz
 +
|freq_avx2_1=3,800MHz
 +
|freq_avx2_2=3,800MHz
 +
|freq_avx2_3=3,600MHz
 +
|freq_avx2_4=3,600MHz
 +
|freq_avx2_5=3,500MHz
 +
|freq_avx2_6=3,500MHz
 +
|freq_avx2_7=3,500MHz
 +
|freq_avx2_8=3,500MHz
 +
|freq_avx2_9=3,400MHz
 +
|freq_avx2_10=3,400MHz
 +
|freq_avx2_11=3,400MHz
 +
|freq_avx2_12=3,400MHz
 +
|freq_avx2_13=3,000MHz
 +
|freq_avx2_14=3,000MHz
 +
|freq_avx2_15=3,000MHz
 +
|freq_avx2_16=3,000MHz
 +
|freq_avx2_17=2,800MHz
 +
|freq_avx2_18=2,800MHz
 +
|freq_avx2_19=2,800MHz
 +
|freq_avx2_20=2,800MHz
 +
|freq_avx512_base=1,100MHz
 +
|freq_avx512_1=3,200MHz
 +
|freq_avx512_2=3,200MHz
 +
|freq_avx512_3=3,000MHz
 +
|freq_avx512_4=3,000MHz
 +
|freq_avx512_5=2,800MHz
 +
|freq_avx512_6=2,800MHz
 +
|freq_avx512_7=2,800MHz
 +
|freq_avx512_8=2,800MHz
 +
|freq_avx512_9=2,400MHz
 +
|freq_avx512_10=2,400MHz
 +
|freq_avx512_11=2,400MHz
 +
|freq_avx512_12=2,400MHz
 +
|freq_avx512_13=2,200MHz
 +
|freq_avx512_14=2,200MHz
 +
|freq_avx512_15=2,200MHz
 +
|freq_avx512_16=2,200MHz
 +
|freq_avx512_17=2,000MHz
 +
|freq_avx512_18=2,000MHz
 +
|freq_avx512_19=2,000MHz
 +
|freq_avx512_20=2,000MHz
 +
|freq_avx512_21=1,900MHz
 +
|freq_avx512_22=1,900MHz
 +
|freq_avx512_23=1,900MHz
 +
|freq_avx512_24=1,900MHz
 +
}}

Latest revision as of 01:18, 29 December 2019

Edit Values
Xeon Gold 6262V
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6262V
S-SpecQS2B (QS)
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$2,900.00 (tray)
ShopAmazon
General Specs
FamilyXeon Gold
Series6200
LockedYes
Frequency1,900 MHz
Turbo Frequency3,600 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier19
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core Model85
Core SteppingB1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores24
Threads48
Max Memory1 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP135 W
Tcase0 °C – 91 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Gold 6262V is a 64-bit 24-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6262V is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 1.9 GHz with a TDP of 135 W and features a turbo boost frequency of up to 3.6 GHz.


Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$768 KiB
786,432 B
0.75 MiB
24x32 KiB8-way set associative 
L1D$768 KiB
786,432 B
0.75 MiB
24x32 KiB8-way set associativewrite-back
L2$24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
  24x1 MiB16-way set associativewrite-back
L3$33 MiB
33,792 KiB
34,603,008 B
0.0322 GiB
  24x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112131415161718192021222324
Normal1,900MHz3,600MHz3,600MHz3,400MHz3,400MHz3,300MHz3,300MHz3,300MHz3,300MHz3,200MHz3,200MHz3,200MHz3,200MHz2,900MHz2,900MHz2,900MHz2,900MHz2,600MHz2,600MHz2,600MHz2,600MHz2,500MHz2,500MHz2,500MHz2,500MHz
AVX21,600MHz3,800MHz3,800MHz3,600MHz3,600MHz3,500MHz3,500MHz3,500MHz3,500MHz3,400MHz3,400MHz3,400MHz3,400MHz3,000MHz3,000MHz3,000MHz3,000MHz2,800MHz2,800MHz2,800MHz2,800MHz
AVX5121,100MHz3,200MHz3,200MHz3,000MHz3,000MHz2,800MHz2,800MHz2,800MHz2,800MHz2,400MHz2,400MHz2,400MHz2,400MHz2,200MHz2,200MHz2,200MHz2,200MHz2,000MHz2,000MHz2,000MHz2,000MHz1,900MHz1,900MHz1,900MHz1,900MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6262v&oldid=95173"
Facts about "Xeon Gold 6262V - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6262V - Intel#pcie +
base frequency1,900 MHz (1.9 GHz, 1,900,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier19 +
core count24 +
core family6 +
core model85 +
core nameCascade Lake SP +
core steppingB1 +
designerIntel +
familyXeon Gold +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon gold/6262v +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description8-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description16-way set associative +
l2$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ description11-way set associative +
l3$ size33 MiB (33,792 KiB, 34,603,008 B, 0.0322 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature364.15 K (91 °C, 195.8 °F, 655.47 °R) +
max cpu count4 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number6262V +
nameXeon Gold 6262V +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 2,900.00 (€ 2,610.00, £ 2,349.00, ¥ 299,657.00) +
release price (tray)$ 2,900.00 (€ 2,610.00, £ 2,349.00, ¥ 299,657.00) +
s-spec (qs)QS2B +
series6200 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2400 +
tdp135 W (135,000 mW, 0.181 hp, 0.135 kW) +
technologyCMOS +
thread count48 +
turbo frequency (1 core)3,600 MHz (3.6 GHz, 3,600,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +