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Difference between revisions of "intel/xeon gold/6246"
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|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=6246
 
|model number=6246
 +
|s-spec qs=QS1Q
 
|market=Server
 
|market=Server
 
|first announced=April 2, 2019
 
|first announced=April 2, 2019
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|core family=6
 
|core family=6
 
|core model=85
 
|core model=85
 +
|core stepping=B1
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
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|core count=12
 
|core count=12
 
|thread count=24
 
|thread count=24
 +
|max memory=1 TiB
 
|max cpus=4
 
|max cpus=4
−
|max memory=1 TiB
+
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 
|tdp=165 W
 
|tdp=165 W
 
|tcase min=0 °C
 
|tcase min=0 °C

Latest revision as of 02:17, 29 December 2019

Edit Values
Xeon Gold 6246
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6246
S-SpecQS1Q (QS)
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$3,286.00 (tray)
ShopAmazon
General Specs
FamilyXeon Gold
Series6200
LockedYes
Frequency3,300 MHz
Turbo Frequency4,200 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier33
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core Model85
Core SteppingB1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores12
Threads24
Max Memory1 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP165 W
Tcase0 °C – 76 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 6246 is a 64-bit 12-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6246 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.3 GHz with a TDP of 165 W and features a turbo boost frequency of up to 4.2 GHz.


Cache[edit]

Main article: Cascade Lake § Cache

The Xeon Gold 6246 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back
L3$24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
  18x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth131.13 GiB/s
134,277.12 MiB/s
140.8 GB/s
140,799.765 MB/s
0.128 TiB/s
0.141 TB/s
Bandwidth
Single 21.86 GiB/s
Double 43.71 GiB/s
Quad 87.42 GiB/s
Hexa 131.13 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112
Normal3,300MHz4,200MHz4,200MHz4,100MHz4,100MHz4,100MHz4,100MHz4,100MHz4,100MHz4,100MHz4,100MHz4,100MHz4,100MHz
AVX22,900MHz4,000MHz4,000MHz3,800MHz3,800MHz3,800MHz3,800MHz3,800MHz3,800MHz3,800MHz3,800MHz3,800MHz3,800MHz
AVX5122,400MHz3,900MHz3,900MHz3,700MHz3,700MHz3,600MHz3,600MHz3,600MHz3,600MHz3,400MHz3,400MHz3,400MHz3,400MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6246&oldid=95168"
Facts about "Xeon Gold 6246 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6246 - Intel#pcie +
base frequency3,300 MHz (3.3 GHz, 3,300,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier33 +
core count12 +
core family6 +
core model85 +
core nameCascade Lake SP +
core steppingB1 +
designerIntel +
familyXeon Gold +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon gold/6246 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature349.15 K (76 °C, 168.8 °F, 628.47 °R) +
max cpu count4 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number6246 +
nameXeon Gold 6246 +
packageFCLGA-3647 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 3,286.00 (€ 2,957.40, £ 2,661.66, ¥ 339,542.38) +
release price (tray)$ 3,286.00 (€ 2,957.40, £ 2,661.66, ¥ 339,542.38) +
s-spec (qs)QS1Q +
series6200 +
smp interconnectUPI +
smp interconnect links3 +
smp interconnect rate10.4 GT/s +
smp max ways4 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2933 +
tdp165 W (165,000 mW, 0.221 hp, 0.165 kW) +
technologyCMOS +
thread count24 +
turbo frequency (1 core)4,200 MHz (4.2 GHz, 4,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +