From WikiChip
Difference between revisions of "intel/xeon gold/6246"
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|manufacturer=Intel | |manufacturer=Intel | ||
|model number=6246 | |model number=6246 | ||
+ | |s-spec qs=QS1Q | ||
|market=Server | |market=Server | ||
|first announced=April 2, 2019 | |first announced=April 2, 2019 | ||
Line 27: | Line 28: | ||
|core family=6 | |core family=6 | ||
|core model=85 | |core model=85 | ||
+ | |core stepping=B1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 32: | Line 34: | ||
|core count=12 | |core count=12 | ||
|thread count=24 | |thread count=24 | ||
+ | |max memory=1 TiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=165 W | |tdp=165 W | ||
|tcase min=0 °C | |tcase min=0 °C |
Latest revision as of 02:17, 29 December 2019
Edit Values | |
Xeon Gold 6246 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6246 |
S-Spec | QS1Q (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $3,286.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6200 |
Locked | Yes |
Frequency | 3,300 MHz |
Turbo Frequency | 4,200 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 33 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Model | 85 |
Core Stepping | B1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 165 W |
Tcase | 0 °C – 76 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 6246 is a 64-bit 12-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6246 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.3 GHz with a TDP of 165 W and features a turbo boost frequency of up to 4.2 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
The Xeon Gold 6246 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 3,300MHz | 4,200MHz | 4,200MHz | 4,100MHz | 4,100MHz | 4,100MHz | 4,100MHz | 4,100MHz | 4,100MHz | 4,100MHz | 4,100MHz | 4,100MHz | 4,100MHz |
AVX2 | 2,900MHz | 4,000MHz | 4,000MHz | 3,800MHz | 3,800MHz | 3,800MHz | 3,800MHz | 3,800MHz | 3,800MHz | 3,800MHz | 3,800MHz | 3,800MHz | 3,800MHz |
AVX512 | 2,400MHz | 3,900MHz | 3,900MHz | 3,700MHz | 3,700MHz | 3,600MHz | 3,600MHz | 3,600MHz | 3,600MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz |
Facts about "Xeon Gold 6246 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6246 - Intel#pcie + |
base frequency | 3,300 MHz (3.3 GHz, 3,300,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 33 + |
core count | 12 + |
core family | 6 + |
core model | 85 + |
core name | Cascade Lake SP + |
core stepping | B1 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/6246 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
ldate | April 2, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 349.15 K (76 °C, 168.8 °F, 628.47 °R) + |
max cpu count | 4 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 6246 + |
name | Xeon Gold 6246 + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 3,286.00 (€ 2,957.40, £ 2,661.66, ¥ 339,542.38) + |
release price (tray) | $ 3,286.00 (€ 2,957.40, £ 2,661.66, ¥ 339,542.38) + |
s-spec (qs) | QS1Q + |
series | 6200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2933 + |
tdp | 165 W (165,000 mW, 0.221 hp, 0.165 kW) + |
technology | CMOS + |
thread count | 24 + |
turbo frequency (1 core) | 4,200 MHz (4.2 GHz, 4,200,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |