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Difference between revisions of "intel/xeon gold/6244"
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{{chip
 
{{chip
 
|name=Xeon Gold 6244
 
|name=Xeon Gold 6244
−
|image=skylake sp (basic).png
+
|image=cascade lake sp (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=6244
 
|model number=6244
 +
|part number=CD8069504194202
 +
|s-spec=SRF8Z
 +
|s-spec qs=QRAJ
 
|market=Server
 
|market=Server
−
|first announced=March, 2019
+
|first announced=April 2, 2019
−
|first launched=March, 2019
+
|first launched=April 2, 2019
 +
|release price (tray)=$2,925.00
 
|family=Xeon Gold
 
|family=Xeon Gold
−
|series=6000
+
|series=6200
 
|locked=Yes
 
|locked=Yes
 
|frequency=3,600 MHz
 
|frequency=3,600 MHz
 
|turbo frequency1=4,400 MHz
 
|turbo frequency1=4,400 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 
|clock multiplier=36
 
|clock multiplier=36
 
|isa=x86-64
 
|isa=x86-64
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|core name=Cascade Lake SP
 
|core name=Cascade Lake SP
 
|core family=6
 
|core family=6
 +
|core model=85
 +
|core stepping=B0
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
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|core count=8
 
|core count=8
 
|thread count=16
 
|thread count=16
 +
|max memory=1 TiB
 
|max cpus=4
 
|max cpus=4
 +
|smp interconnect=UPI
 +
|smp interconnect links=3
 +
|smp interconnect rate=10.4 GT/s
 
|tdp=150 W
 
|tdp=150 W
 
|tcase min=0 °C
 
|tcase min=0 °C
−
|tcase max=75 °C
+
|tcase max=74 °C
−
|dts min=0 °C
+
|package name 1=intel,fclga_3647
−
|dts max=102 °C
+
|predecessor=Xeon Gold 6144
−
|package module 1={{packages/intel/fclga-3647}}
+
|predecessor link=intel/xeon_gold/6144
 
}}
 
}}
−
'''Xeon Gold 6244''' is a {{arch|64}} [[octa-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6244, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.6 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 4.4 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
+
'''Xeon Gold 6244''' is a {{arch|64}} [[octa-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6244 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.6 GHz with a TDP of 150 W and features a {{intel|turbo boost}} frequency of up to 4.4 GHz.
 +
 
  
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
+
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 
The Xeon Gold 6244 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part.
 
The Xeon Gold 6244 features a considerably larger non-default 24.75 MiB of [[L3]], a size that would normally be found on an 18-core part.
 
{{cache size
 
{{cache size
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== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=DDR4-2666
+
|type=DDR4-2933
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=? GiB
+
|max mem=1 TiB
 
|controllers=2
 
|controllers=2
 
|channels=6
 
|channels=6
−
|max bandwidth=119.21 GiB/s
+
|max bandwidth=131.13 GiB/s
−
|bandwidth schan=19.87 GiB/s
+
|bandwidth schan=21.86 GiB/s
−
|bandwidth dchan=39.74 GiB/s
+
|bandwidth dchan=43.71 GiB/s
−
|bandwidth qchan=79.47 GiB/s
+
|bandwidth qchan=87.42 GiB/s
−
|bandwidth hchan=119.21 GiB/s
+
|bandwidth hchan=131.13 GiB/s
 
}}
 
}}
  
 
== Expansions ==
 
== Expansions ==
−
{{expansions
+
{{expansions main
−
| pcie revision     = 3.0
+
|
−
| pcie lanes         = 48
+
{{expansions entry
−
| pcie config       = x16
+
|type=PCIe
−
| pcie config 2     = x8
+
|pcie revision=3.0
−
| pcie config 3     = x4
+
|pcie lanes=48
 +
|pcie config=1x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 
}}
 
}}
  
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|avx512vbmi=No
 
|avx512vbmi=No
 
|avx5124fmaps=No
 
|avx5124fmaps=No
 +
|avx512vnni=Yes
 
|avx5124vnniw=No
 
|avx5124vnniw=No
 
|avx512vpopcntdq=No
 
|avx512vpopcntdq=No
Line 128: Line 147:
 
|clmul=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|f16c=Yes
 +
|bfloat16=No
 
|tbt1=No
 
|tbt1=No
 
|tbt2=Yes
 
|tbt2=Yes
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|fastmem=No
 
|fastmem=No
 
|ivmd=Yes
 
|ivmd=Yes
−
|intelnodecontroller=Yes
+
|intelnodecontroller=No
 
|intelnode=Yes
 
|intelnode=Yes
 
|kpt=Yes
 
|kpt=Yes
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|securekey=No
 
|securekey=No
 
|osguard=No
 
|osguard=No
 +
|intqat=No
 +
|dlboost=Yes
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
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|sensemi=No
 
|sensemi=No
 
|xfr=No
 
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=3,600MHz
 +
|freq_1=4,400MHz
 +
|freq_2=4,400MHz
 +
|freq_3=4,300MHz
 +
|freq_4=4,300MHz
 +
|freq_5=4,300MHz
 +
|freq_6=4,300MHz
 +
|freq_7=4,300MHz
 +
|freq_8=4,300MHz
 +
|freq_avx2_base=3,000MHz
 +
|freq_avx2_1=4,000MHz
 +
|freq_avx2_2=4,000MHz
 +
|freq_avx2_3=3,900MHz
 +
|freq_avx2_4=3,900MHz
 +
|freq_avx2_5=3,900MHz
 +
|freq_avx2_6=3,900MHz
 +
|freq_avx2_7=3,900MHz
 +
|freq_avx2_8=3,900MHz
 +
|freq_avx512_base=2,600MHz
 +
|freq_avx512_1=3,800MHz
 +
|freq_avx512_2=3,800MHz
 +
|freq_avx512_3=3,600MHz
 +
|freq_avx512_4=3,600MHz
 +
|freq_avx512_5=3,500MHz
 +
|freq_avx512_6=3,500MHz
 +
|freq_avx512_7=3,500MHz
 +
|freq_avx512_8=3,500MHz
 
}}
 
}}

Latest revision as of 01:17, 29 December 2019

Edit Values
Xeon Gold 6244
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number6244
Part NumberCD8069504194202
S-SpecSRF8Z
QRAJ (QS)
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$2,925.00 (tray)
ShopAmazon
General Specs
FamilyXeon Gold
Series6200
LockedYes
Frequency3,600 MHz
Turbo Frequency4,400 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier36
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core Model85
Core SteppingB0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads16
Max Memory1 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
InterconnectUPI
Interconnect Links3
Interconnect Rate10.4 GT/s
Electrical
TDP150 W
Tcase0 °C – 74 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Gold 6244 is a 64-bit octa-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6244 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.6 GHz with a TDP of 150 W and features a turbo boost frequency of up to 4.4 GHz.


Cache[edit]

Main article: Cascade Lake § Cache

The Xeon Gold 6244 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$24.75 MiB
25,344 KiB
25,952,256 B
0.0242 GiB
  18x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth131.13 GiB/s
134,277.12 MiB/s
140.8 GB/s
140,799.765 MB/s
0.128 TiB/s
0.141 TB/s
Bandwidth
Single 21.86 GiB/s
Double 43.71 GiB/s
Quad 87.42 GiB/s
Hexa 131.13 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678
Normal3,600MHz4,400MHz4,400MHz4,300MHz4,300MHz4,300MHz4,300MHz4,300MHz4,300MHz
AVX23,000MHz4,000MHz4,000MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz3,900MHz
AVX5122,600MHz3,800MHz3,800MHz3,600MHz3,600MHz3,500MHz3,500MHz3,500MHz3,500MHz
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