From WikiChip
Difference between revisions of "intel/xeon gold/5218t"
(8 intermediate revisions by the same user not shown) | |||
Line 6: | Line 6: | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=5218T | |model number=5218T | ||
+ | |s-spec qs=QS1T | ||
|market=Server | |market=Server | ||
|first announced=April 2, 2019 | |first announced=April 2, 2019 | ||
|first launched=April 2, 2019 | |first launched=April 2, 2019 | ||
+ | |release price (tray)=$1561.00 | ||
+ | |release price (box)=$1555.00 | ||
|family=Xeon Gold | |family=Xeon Gold | ||
|series=5200 | |series=5200 | ||
|locked=Yes | |locked=Yes | ||
|frequency=2,100 MHz | |frequency=2,100 MHz | ||
+ | |turbo frequency1=3,800 MHz | ||
|bus type=DMI 3.0 | |bus type=DMI 3.0 | ||
|bus links=4 | |bus links=4 | ||
Line 25: | Line 29: | ||
|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
+ | |core stepping=B1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 30: | Line 35: | ||
|core count=16 | |core count=16 | ||
|thread count=32 | |thread count=32 | ||
+ | |max memory=1 TiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=105 W | |tdp=105 W | ||
|package name 1=intel,fclga_3647 | |package name 1=intel,fclga_3647 | ||
}} | }} | ||
− | '''Xeon Gold 5218T''' is a {{arch|64}} [[16-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5218T is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as | + | '''Xeon Gold 5218T''' is a {{arch|64}} [[16-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5218T is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.1 GHz with a TDP of 105 W and features a {{intel|turbo boost}} frequency of up to 3.8 GHz. |
+ | |||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1 MiB | ||
+ | |l1i cache=512 KiB | ||
+ | |l1i break=16x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=512 KiB | ||
+ | |l1d break=16x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=16 MiB | ||
+ | |l2 break=16x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=22 MiB | ||
+ | |l3 break=16x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=1 TiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=119.21 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=48 | ||
+ | |pcie config=1x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=Yes | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |bfloat16=No | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=No | ||
+ | |mbe=Yes | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,100MHz | ||
+ | |freq_1=3,800MHz | ||
+ | |freq_2=3,800MHz | ||
+ | |freq_3=3,600MHz | ||
+ | |freq_4=3,600MHz | ||
+ | |freq_5=3,500MHz | ||
+ | |freq_6=3,500MHz | ||
+ | |freq_7=3,500MHz | ||
+ | |freq_8=3,500MHz | ||
+ | |freq_9=3,000MHz | ||
+ | |freq_10=3,000MHz | ||
+ | |freq_11=3,000MHz | ||
+ | |freq_12=3,000MHz | ||
+ | |freq_13=2,700MHz | ||
+ | |freq_14=2,700MHz | ||
+ | |freq_15=2,700MHz | ||
+ | |freq_16=2,700MHz | ||
+ | |freq_avx2_base=1,700MHz | ||
+ | |freq_avx2_1=2,800MHz | ||
+ | |freq_avx2_2=2,800MHz | ||
+ | |freq_avx2_3=2,600MHz | ||
+ | |freq_avx2_4=2,600MHz | ||
+ | |freq_avx2_5=2,500MHz | ||
+ | |freq_avx2_6=2,500MHz | ||
+ | |freq_avx2_7=2,500MHz | ||
+ | |freq_avx2_8=2,500MHz | ||
+ | |freq_avx2_9=2,400MHz | ||
+ | |freq_avx2_10=2,400MHz | ||
+ | |freq_avx2_11=2,400MHz | ||
+ | |freq_avx2_12=2,400MHz | ||
+ | |freq_avx2_13=2,200MHz | ||
+ | |freq_avx2_14=2,200MHz | ||
+ | |freq_avx2_15=2,200MHz | ||
+ | |freq_avx2_16=2,200MHz | ||
+ | |freq_avx512_base=1,300MHz | ||
+ | |freq_avx512_1=2,800MHz | ||
+ | |freq_avx512_2=2,800MHz | ||
+ | |freq_avx512_3=2,600MHz | ||
+ | |freq_avx512_4=2,600MHz | ||
+ | |freq_avx512_5=2,500MHz | ||
+ | |freq_avx512_6=2,500MHz | ||
+ | |freq_avx512_7=2,500MHz | ||
+ | |freq_avx512_8=2,500MHz | ||
+ | |freq_avx512_9=2,200MHz | ||
+ | |freq_avx512_10=2,200MHz | ||
+ | |freq_avx512_11=2,200MHz | ||
+ | |freq_avx512_12=2,200MHz | ||
+ | |freq_avx512_13=2,000MHz | ||
+ | |freq_avx512_14=2,000MHz | ||
+ | |freq_avx512_15=2,000MHz | ||
+ | |freq_avx512_16=2,000MHz | ||
+ | }} |
Latest revision as of 23:22, 28 December 2019
Edit Values | |
Xeon Gold 5218T | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 5218T |
S-Spec | QS1T (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $1561.00 (tray) $1555.00 (box) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 5200 |
Locked | Yes |
Frequency | 2,100 MHz |
Turbo Frequency | 3,800 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 21 |
CPUID | 0x50655 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Stepping | B1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 16 |
Threads | 32 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 105 W |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Gold 5218T is a 64-bit 16-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5218T is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.1 GHz with a TDP of 105 W and features a turbo boost frequency of up to 3.8 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
Integrated Memory Controller
|
||||||||||||||
|
Expansions[edit]
Expansion Options |
|||||
|
Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | ||
Normal | 2,100MHz | 3,800MHz | 3,800MHz | 3,600MHz | 3,600MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,000MHz | 3,000MHz | 3,000MHz | 3,000MHz | 2,700MHz | 2,700MHz | 2,700MHz | 2,700MHz |
AVX2 | 1,700MHz | 2,800MHz | 2,800MHz | 2,600MHz | 2,600MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,400MHz | 2,400MHz | 2,400MHz | 2,400MHz | 2,200MHz | 2,200MHz | 2,200MHz | 2,200MHz |
AVX512 | 1,300MHz | 2,800MHz | 2,800MHz | 2,600MHz | 2,600MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,200MHz | 2,200MHz | 2,200MHz | 2,200MHz | 2,000MHz | 2,000MHz | 2,000MHz | 2,000MHz |
Facts about "Xeon Gold 5218T - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5218T - Intel#pcie + |
base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 21 + |
core count | 16 + |
core family | 6 + |
core name | Cascade Lake SP + |
core stepping | B1 + |
cpuid | 0x50655 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/5218t + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
ldate | April 2, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max cpu count | 4 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
model number | 5218T + |
name | Xeon Gold 5218T + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,561.00 (€ 1,404.90, £ 1,264.41, ¥ 161,298.13) + and $ 1,555.00 (€ 1,399.50, £ 1,259.55, ¥ 160,678.15) + |
release price (box) | $ 1,555.00 (€ 1,399.50, £ 1,259.55, ¥ 160,678.15) + |
release price (tray) | $ 1,561.00 (€ 1,404.90, £ 1,264.41, ¥ 161,298.13) + |
s-spec (qs) | QS1T + |
series | 5200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
technology | CMOS + |
thread count | 32 + |
turbo frequency (1 core) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |