From WikiChip
Difference between revisions of "intel/xeon gold/5217"
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|part number=CD8069504214302 | |part number=CD8069504214302 | ||
|s-spec=SRFBF | |s-spec=SRFBF | ||
+ | |s-spec qs=QRGC | ||
|market=Server | |market=Server | ||
|first announced=April 2, 2019 | |first announced=April 2, 2019 | ||
Line 29: | Line 30: | ||
|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
− | |core stepping=L1 | + | |core stepping=L0 |
+ | |core stepping 2=L1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 35: | Line 37: | ||
|core count=8 | |core count=8 | ||
|thread count=16 | |thread count=16 | ||
+ | |max memory=1 TiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=115 W | |tdp=115 W | ||
|package name 1=intel,fclga_3647 | |package name 1=intel,fclga_3647 | ||
+ | |predecessor=Xeon Gold 5117 | ||
+ | |predecessor link=intel/xeon_gold/5117 | ||
}} | }} | ||
− | '''Xeon Gold 5217''' is a {{arch|64}} [[octa-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5217 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as | + | '''Xeon Gold 5217''' is a {{arch|64}} [[octa-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5217 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 3 GHz with a TDP of 115 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz. |
Line 191: | Line 198: | ||
|amdpb2=No | |amdpb2=No | ||
|amdpbod=No | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=3,000MHz | ||
+ | |freq_1=3,700MHz | ||
+ | |freq_2=3,700MHz | ||
+ | |freq_3=3,500MHz | ||
+ | |freq_4=3,500MHz | ||
+ | |freq_5=3,400MHz | ||
+ | |freq_6=3,400MHz | ||
+ | |freq_7=3,400MHz | ||
+ | |freq_8=3,400MHz | ||
+ | |freq_avx2_base=2,500MHz | ||
+ | |freq_avx2_1=3,500MHz | ||
+ | |freq_avx2_2=3,500MHz | ||
+ | |freq_avx2_3=3,300MHz | ||
+ | |freq_avx2_4=3,300MHz | ||
+ | |freq_avx2_5=3,000MHz | ||
+ | |freq_avx2_6=3,000MHz | ||
+ | |freq_avx2_7=3,000MHz | ||
+ | |freq_avx2_8=3,000MHz | ||
+ | |freq_avx512_base=2,000MHz | ||
+ | |freq_avx512_1=2,900MHz | ||
+ | |freq_avx512_2=2,900MHz | ||
+ | |freq_avx512_3=2,700MHz | ||
+ | |freq_avx512_4=2,700MHz | ||
+ | |freq_avx512_5=2,400MHz | ||
+ | |freq_avx512_6=2,400MHz | ||
+ | |freq_avx512_7=2,400MHz | ||
+ | |freq_avx512_8=2,400MHz | ||
}} | }} |
Latest revision as of 23:43, 28 December 2019
Edit Values | |
Xeon Gold 5217 | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 5217 |
Part Number | CD8069504214302 |
S-Spec | SRFBF QRGC (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $1,522.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 5200 |
Locked | Yes |
Frequency | 3,000 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 30 |
CPUID | 0x50655 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Stepping | L0, L1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 115 W |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Gold 5217 is a 64-bit octa-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5217 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 3 GHz with a TDP of 115 W and features a turbo boost frequency of up to 3.7 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||
---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | ||
Normal | 3,000MHz | 3,700MHz | 3,700MHz | 3,500MHz | 3,500MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz |
AVX2 | 2,500MHz | 3,500MHz | 3,500MHz | 3,300MHz | 3,300MHz | 3,000MHz | 3,000MHz | 3,000MHz | 3,000MHz |
AVX512 | 2,000MHz | 2,900MHz | 2,900MHz | 2,700MHz | 2,700MHz | 2,400MHz | 2,400MHz | 2,400MHz | 2,400MHz |
Facts about "Xeon Gold 5217 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5217 - Intel#pcie + |
base frequency | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 30 + |
core count | 8 + |
core family | 6 + |
core name | Cascade Lake SP + |
core stepping | L0 + and L1 + |
cpuid | 0x50655 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/5217 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) + |
ldate | April 2, 2019 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max cpu count | 4 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
model number | 5217 + |
name | Xeon Gold 5217 + |
package | FCLGA-3647 + |
part number | CD8069504214302 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,522.00 (€ 1,369.80, £ 1,232.82, ¥ 157,268.26) + |
release price (tray) | $ 1,522.00 (€ 1,369.80, £ 1,232.82, ¥ 157,268.26) + |
s-spec | SRFBF + |
s-spec (qs) | QRGC + |
series | 5200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2666 + |
tdp | 115 W (115,000 mW, 0.154 hp, 0.115 kW) + |
technology | CMOS + |
thread count | 16 + |
turbo frequency (1 core) | 3,700 MHz (3.7 GHz, 3,700,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |