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Difference between revisions of "intel/xeon w/w-3265"
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{{intel title|Xeon W-3265}} | {{intel title|Xeon W-3265}} | ||
− | {{chip}} | + | {{chip |
+ | |name=Xeon W-3265 | ||
+ | |image=cascade lake sp (xeon w) (front).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=W-3265 | ||
+ | |part number=CD8069504153002 | ||
+ | |s-spec=SRFFE | ||
+ | |market=Workstation | ||
+ | |first announced=June 3, 2019 | ||
+ | |first launched=June 3, 2019 | ||
+ | |release price (tray)=$3349.00 | ||
+ | |family=Xeon W | ||
+ | |series=W-3200 | ||
+ | |locked=Yes | ||
+ | |frequency=2,700 MHz | ||
+ | |turbo frequency1=4,400 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=27 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Cascade Lake | ||
+ | |core name=Cascade Lake SP | ||
+ | |core stepping=B1 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=24 | ||
+ | |thread count=48 | ||
+ | |max cpus=1 | ||
+ | |max memory=1 TiB | ||
+ | |tdp=205 W | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | }} | ||
+ | '''W-3265''' is a {{arch|64}} [[24-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processor is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture. The W-3265 operates at 2.7 GHz with a [[TDP]] of 205 W, a {{intel|turbo boost}} frequency of up to 4.4 GHz and a {{intel|turbo boost max}} of 4.6 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2933 memory. | ||
+ | |||
+ | |||
+ | {{#set:intel turbo boost max technology 3 0 frequency=4.6 GHz}} | ||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1.5 MiB | ||
+ | |l1i cache=768 KiB | ||
+ | |l1i break=24x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=768 KiB | ||
+ | |l1d break=24x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=24 MiB | ||
+ | |l2 break=24x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=33 MiB | ||
+ | |l3 break=24x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2933 | ||
+ | |ecc=Yes | ||
+ | |max mem=1 TiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=131.13 GiB/s | ||
+ | |bandwidth schan=21.86 GiB/s | ||
+ | |bandwidth dchan=43.71 GiB/s | ||
+ | |bandwidth qchan=87.42 GiB/s | ||
+ | |bandwidth hchan=131.13 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=64 | ||
+ | |pcie config=x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | |pcie config 4=x1 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,500 MHz | ||
+ | |freq_1=4,600 MHz | ||
+ | |freq_2=4,600 MHz | ||
+ | |freq_3=4,400 MHz | ||
+ | |freq_4=4,400 MHz | ||
+ | |freq_5=4,100 MHz | ||
+ | |freq_6=4,100 MHz | ||
+ | |freq_7=4,100 MHz | ||
+ | |freq_8=4,100 MHz | ||
+ | |freq_9=4,100 MHz | ||
+ | |freq_10=4,100 MHz | ||
+ | |freq_11=4,100 MHz | ||
+ | |freq_12=4,100 MHz | ||
+ | |freq_13=3,900 MHz | ||
+ | |freq_14=3,900 MHz | ||
+ | |freq_15=3,900 MHz | ||
+ | |freq_16=3,900 MHz | ||
+ | |freq_17=3,600 MHz | ||
+ | |freq_18=3,600 MHz | ||
+ | |freq_19=3,600 MHz | ||
+ | |freq_20=3,600 MHz | ||
+ | |freq_21=3,400 MHz | ||
+ | |freq_22=3,400 MHz | ||
+ | |freq_23=3,400 MHz | ||
+ | |freq_24=3,400 MHz | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=Yes | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |avx512units=2 | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |bfloat16=No | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=Yes | ||
+ | |tvb=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=Yes | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=Yes | ||
+ | |sgx=No | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |intqat=No | ||
+ | |dlboost=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:w-3200-pb.pdf|Xeon W-3200 Series Product Brief]] |
Latest revision as of 14:24, 31 October 2019
Edit Values | |
Xeon W-3265 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | W-3265 |
Part Number | CD8069504153002 |
S-Spec | SRFFE |
Market | Workstation |
Introduction | June 3, 2019 (announced) June 3, 2019 (launched) |
Release Price | $3349.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon W |
Series | W-3200 |
Locked | Yes |
Frequency | 2,700 MHz |
Turbo Frequency | 4,400 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 27 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Core Name | Cascade Lake SP |
Core Stepping | B1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 24 |
Threads | 48 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 205 W |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
W-3265 is a 64-bit 24-core x86 enterprise performance workstation microprocessor introduced by Intel in 2019. This processor is fabricated on an enhanced 14nm++ process based on the Cascade Lake microarchitecture. The W-3265 operates at 2.7 GHz with a TDP of 205 W, a turbo boost frequency of up to 4.4 GHz and a turbo boost max of 4.6 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2933 memory.
Cache[edit]
- Main article: Cascade Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | ||
Normal | 2,500 MHz | 4,600 MHz | 4,600 MHz | 4,400 MHz | 4,400 MHz | 4,100 MHz | 4,100 MHz | 4,100 MHz | 4,100 MHz | 4,100 MHz | 4,100 MHz | 4,100 MHz | 4,100 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz | 3,400 MHz |
Features[edit]
[Edit/Modify Supported Features]
Documents[edit]
Facts about "Xeon W-3265 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon W-3265 - Intel#pcie + |
base frequency | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 27 + |
core count | 24 + |
core name | Cascade Lake SP + |
core stepping | B1 + |
designer | Intel + |
family | Xeon W + |
first announced | June 3, 2019 + |
first launched | June 3, 2019 + |
full page name | intel/xeon w/w-3265 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Turbo Boost Max Technology 3.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard +, Deep Learning Boost + and Identity Protection Technology + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost max technology 3 0 | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
intel turbo boost max technology 3 0 frequency | 4,600 MHz (4.6 GHz, 4,600,000 kHz) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 33 MiB (33,792 KiB, 34,603,008 B, 0.0322 GiB) + |
ldate | June 3, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Workstation + |
max cpu count | 1 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
model number | W-3265 + |
name | Xeon W-3265 + |
number of avx-512 execution units | 2 + |
package | FCLGA-3647 + |
part number | CD8069504153002 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 3,349.00 (€ 3,014.10, £ 2,712.69, ¥ 346,052.17) + |
release price (tray) | $ 3,349.00 (€ 3,014.10, £ 2,712.69, ¥ 346,052.17) + |
s-spec | SRFFE + |
series | W-3200 + |
smp max ways | 1 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2933 + |
tdp | 205 W (205,000 mW, 0.275 hp, 0.205 kW) + |
technology | CMOS + |
thread count | 48 + |
turbo frequency (1 core) | 4,400 MHz (4.4 GHz, 4,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |