From WikiChip
Difference between revisions of "intel/xeon w/w-3245"
(→Memory controller) |
|||
(13 intermediate revisions by the same user not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Xeon W-3245}} | {{intel title|Xeon W-3245}} | ||
{{chip | {{chip | ||
− | |||
|name=Xeon W-3245 | |name=Xeon W-3245 | ||
− | | | + | |image=cascade lake sp (xeon w) (front).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=W-3245 | |model number=W-3245 | ||
|part number=CD8069504152900 | |part number=CD8069504152900 | ||
+ | |s-spec=SRFFD | ||
|market=Workstation | |market=Workstation | ||
+ | |first announced=June 3, 2019 | ||
+ | |first launched=June 3, 2019 | ||
+ | |release price (tray)=$1,999.00 | ||
|family=Xeon W | |family=Xeon W | ||
|series=W-3200 | |series=W-3200 | ||
|locked=Yes | |locked=Yes | ||
|frequency=3,200 MHz | |frequency=3,200 MHz | ||
+ | |turbo frequency1=4,400 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
|clock multiplier=32 | |clock multiplier=32 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
|microarch=Cascade Lake | |microarch=Cascade Lake | ||
− | |core name=Cascade Lake | + | |core name=Cascade Lake SP |
+ | |core stepping=B1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 24: | Line 32: | ||
|thread count=32 | |thread count=32 | ||
|max cpus=1 | |max cpus=1 | ||
+ | |max memory=1 TiB | ||
|tdp=205 W | |tdp=205 W | ||
+ | |package name 1=intel,fclga_3647 | ||
}} | }} | ||
− | '''W-3245''' is a {{arch|64}} [[hexadeca-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This | + | '''W-3245''' is a {{arch|64}} [[hexadeca-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processor is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture. The W-3245 operates at 3.2 GHz with a [[TDP]] of 205 W, a {{intel|turbo boost}} frequency of up to 4.4 GHz and a {{intel|turbo boost max}} of 4.6 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2933 memory. |
− | |||
− | |||
− | {{ | ||
+ | {{#set:intel turbo boost max technology 3 0 frequency=4.6 GHz}} | ||
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=1 MiB | |l1 cache=1 MiB | ||
Line 57: | Line 65: | ||
|type=DDR4-2933 | |type=DDR4-2933 | ||
|ecc=Yes | |ecc=Yes | ||
− | |max mem=1 | + | |max mem=1 TiB |
|controllers=2 | |controllers=2 | ||
|channels=6 | |channels=6 | ||
Line 73: | Line 81: | ||
|type=PCIe | |type=PCIe | ||
|pcie revision=3.0 | |pcie revision=3.0 | ||
− | |pcie lanes= | + | |pcie lanes=64 |
|pcie config=x16 | |pcie config=x16 | ||
|pcie config 2=x8 | |pcie config 2=x8 | ||
Line 112: | Line 120: | ||
|avx512vbmi=No | |avx512vbmi=No | ||
|avx5124fmaps=No | |avx5124fmaps=No | ||
+ | |avx512vnni=Yes | ||
|avx5124vnniw=No | |avx5124vnniw=No | ||
|avx512vpopcntdq=No | |avx512vpopcntdq=No | ||
Line 128: | Line 137: | ||
|clmul=Yes | |clmul=Yes | ||
|f16c=Yes | |f16c=Yes | ||
+ | |bfloat16=No | ||
|tbt1=No | |tbt1=No | ||
|tbt2=Yes | |tbt2=Yes | ||
− | |tbmt3=No | + | |tbmt3=Yes |
+ | |tvb=No | ||
|bpt=No | |bpt=No | ||
|eist=Yes | |eist=Yes | ||
Line 161: | Line 172: | ||
|osguard=Yes | |osguard=Yes | ||
|intqat=No | |intqat=No | ||
+ | |dlboost=Yes | ||
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 174: | Line 186: | ||
|sensemi=No | |sensemi=No | ||
|xfr=No | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
}} | }} | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:w-3200-pb.pdf|Xeon W-3200 Series Product Brief]] |
Latest revision as of 00:26, 7 October 2019
Edit Values | |
Xeon W-3245 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | W-3245 |
Part Number | CD8069504152900 |
S-Spec | SRFFD |
Market | Workstation |
Introduction | June 3, 2019 (announced) June 3, 2019 (launched) |
Release Price | $1,999.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon W |
Series | W-3200 |
Locked | Yes |
Frequency | 3,200 MHz |
Turbo Frequency | 4,400 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 32 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Core Name | Cascade Lake SP |
Core Stepping | B1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 16 |
Threads | 32 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 205 W |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
W-3245 is a 64-bit hexadeca-core x86 enterprise performance workstation microprocessor introduced by Intel in 2019. This processor is fabricated on an enhanced 14nm++ process based on the Cascade Lake microarchitecture. The W-3245 operates at 3.2 GHz with a TDP of 205 W, a turbo boost frequency of up to 4.4 GHz and a turbo boost max of 4.6 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2933 memory.
Cache[edit]
- Main article: Cascade Lake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions[edit]
![]() |
Expansion Options |
||||
|
Features[edit]
[Edit/Modify Supported Features]
Documents[edit]
Facts about "Xeon W-3245 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon W-3245 - Intel#pcie + |
base frequency | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 32 + |
core count | 16 + |
core name | Cascade Lake SP + |
core stepping | B1 + |
designer | Intel + |
family | Xeon W + |
first announced | June 3, 2019 + |
first launched | June 3, 2019 + |
full page name | intel/xeon w/w-3245 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Turbo Boost Max Technology 3.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard +, Deep Learning Boost + and Identity Protection Technology + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost max technology 3 0 | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
intel turbo boost max technology 3 0 frequency | 4,600 MHz (4.6 GHz, 4,600,000 kHz) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
ldate | June 3, 2019 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Workstation + |
max cpu count | 1 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
model number | W-3245 + |
name | Xeon W-3245 + |
number of avx-512 execution units | 2 + |
package | FCLGA-3647 + |
part number | CD8069504152900 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,999.00 (€ 1,799.10, £ 1,619.19, ¥ 206,556.67) + |
release price (tray) | $ 1,999.00 (€ 1,799.10, £ 1,619.19, ¥ 206,556.67) + |
s-spec | SRFFD + |
series | W-3200 + |
smp max ways | 1 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2933 + |
tdp | 205 W (205,000 mW, 0.275 hp, 0.205 kW) + |
technology | CMOS + |
thread count | 32 + |
turbo frequency (1 core) | 4,400 MHz (4.4 GHz, 4,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |